EOS-Protected Bias Circuits for Thin-Gate Level Shifters
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Solution Overview
Problem
Existing integrated circuit designs face challenges in efficiently managing electrical overstress (EOS) across thin gate transistors while operating at high supply voltages, particularly in multi-supply domains, leading to inefficiencies and potential circuit failures due to excessive power consumption and voltage drops.
Innovation Solution
The implementation of bias circuits that generate resilient output supplies with EOS protection, using thin gate transistors, to maintain consistent bias voltages across a wide range of high supply voltages, minimizing power consumption and preventing EOS violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If thin gate transistors are used to operate at high supply voltages, then circuit integration and voltage handling capability are improved, but electrical overstress (EOS) vulnerability and reliability deteriorate
Solution Approach 1:
The patent introduces an intermediary bias circuit that generates a protected bias voltage (Vb) to control the gate voltages of thin gate transistors. This intermediary circuit acts as a mediator between the high supply voltage domain and the thin gate transistor gates, ensuring that the gate voltages never exceed the maximum rated voltage (Vmax) even when the supply voltage is high. The bias circuit includes voltage division networks and protection transistors that clamp the gate voltages to safe levels, thus resolving the contradiction between high voltage operation and EOS protection.
2Reliability
If bias circuits are added to protect against EOS, then reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent merges the bias generation function with the EOS protection function into a single integrated bias circuit. The same circuit that generates the bias voltage for controlling thin gate transistors also incorporates protection mechanisms to ensure the bias voltage itself does not exceed safe levels. This is achieved by using feedback networks and protection transistors within the bias circuit that automatically clamp voltages to Vmax/2 or Vmax/4 levels. By combining these functions, the patent avoids adding separate protection circuits, thus minimizing the increase in device complexity while maintaining reliability.
3Reliability
If bias circuits are added to protect against EOS, then reliability is improved, but power consumption increases
Solution Approach 1:
The bias circuit is designed to be self-regulating and self-protecting, automatically adjusting its own bias voltages to remain within safe limits without requiring external control. The circuit uses feedback mechanisms where the bias transistors automatically adjust their gate-source voltages based on the supply voltage level, ensuring that internal node voltages never exceed Vmax/2 or Vmax/4. This self-service approach eliminates the need for additional active control circuits that would consume extra power, thus achieving EOS protection with minimal power overhead.
4Adaptability or versatility
If voltage division networks are used to generate bias voltages, then adaptability to different supply voltages is improved, but manufacturing precision requirements increase
Solution Approach 1:
The voltage division networks in the bias circuit are equipped with feedback mechanisms that automatically adjust the division ratios to compensate for manufacturing variations. The feedback is achieved through protection transistors that monitor the divided voltages and adjust their conduction states to ensure that the output voltages remain at the precise levels of Vmax/2 or Vmax/4 regardless of resistor or transistor parameter variations. This feedback approach allows the circuit to adapt to different supply voltages while maintaining precise voltage levels without requiring extremely tight manufacturing tolerances.
Data Source
AI summary
In some embodiments, bias circuits are provided that can generate resilient output supplies without consuming excessive power. In addition, other resilient and efficient bias circuits may be provided that can be used for biasing level shift and other high supply circuit blocks such as LDOs with thin gate transistors over a relatively wide high supply voltage operational range.