Embedded Pattern Generator Circuit for Functional Safety Signal Testing
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Solution Overview
Problem
Software debugging of communication circuitry for functional safety specifications is complex and limited by hardware constraints, requiring high precision waveform generation to test and verify operations, especially in applications like automotive and industrial settings where precise diagnostic and debugging are crucial.
Innovation Solution
An embedded pattern generator circuitry that includes clock divider and signal generator circuitry to produce complex test stimuli, such as skewed clocks and serial data streams, which are hardware-generated to test and debug communication modules, reducing software complexity and improving precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If software based signal generation sequence is used for diagnostic testing, then the communication circuitry can be tested, but the software complexity increases and precision is limited by hardware constraints
Solution Approach 1:
The patent replaces the software-based signal generation system with a hardware-based embedded pattern generator. The EPG circuitry includes clock divider circuitry that divides a system clock into multiple clock outputs, a multiplexer that selects between different clock outputs, and signal generator circuitry that produces test signals. This hardware substitution eliminates software complexity while providing precise waveform generation capability for diagnostic testing of communication circuitry.
2Measurement precision
If high precision waveform generation is implemented to verify communication circuitry operations, then testing precision improves, but device complexity increases
Solution Approach 1:
The embedded pattern generator is designed as a multi-functional hardware circuit that can generate various test waveforms through a unified structure. The clock divider circuitry generates multiple clock outputs from a single system clock, the multiplexer selects between different clock sources, and the signal generator circuitry produces different test signal patterns. This universal design provides high precision waveform generation for multiple diagnostic purposes without requiring separate complex circuitry for each function.
Solution Approach 2:
The EPG circuitry is integrated within the communication circuitry itself, with the pattern generator nested inside the communication module. The multiplexer couples one of the clock outputs to the signal generator circuitry, which is nested within the EPG block that is part of the communication circuitry. This nested integration achieves precise waveform generation while minimizing additional device complexity by embedding the functionality within existing structures.
3Reliability
If software diagnostics are used for functional safety specifications, then diagnostic capability is provided, but the hardware constraints limit the effectiveness
Solution Approach 1:
The patent replaces software-based diagnostic capabilities with a hardware-based embedded pattern generator that is specifically designed for functional safety verification. The EPG circuitry generates precise test signals that can verify communication circuitry operations under various conditions, providing reliable diagnostic capability that is not limited by hardware constraints. The hardware implementation ensures consistent and repeatable test signal generation for safety-critical applications.
Solution Approach 2:
The clock divider circuitry can divide the system clock into multiple different frequency outputs, and the multiplexer can select between different clock division ratios. The signal generator circuitry can generate different test signal patterns and parameters. This ability to change parameters hardware-based provides adaptability for various functional safety verification scenarios while maintaining the reliability needed for safety-critical diagnostic testing.
Data Source
AI summary
An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.