FinFET Epi-RSD Width Expansion Using Sacrificial Liner
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Solution Overview
Problem
Existing FinFET devices face limitations in epitaxial raised source/drain (RSD) width, restricted to 0.7× to 1.3× fin pitch, which hinders performance gains and results in yield loss penalties beyond the 7 nm technology node.
Innovation Solution
The RSD region is grown to a width larger than 1.3× fin pitch using epitaxial growth, with a sacrificial liner and trench silicide formation, allowing for increased performance without yield loss by creating a larger N-P space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epi-RSD width is increased beyond 1.3× fin pitch, then device performance increases, but yield loss occurs due to smaller N-P space
Solution Approach 1:
A sacrificial liner is formed on the exposed side of the epi-RSD before final patterning. This preliminary structure enables subsequent margin removal while protecting the epi-RSD during processing, allowing width >1.3× fin pitch without yield penalty
Solution Approach 2:
The sacrificial liner is selectively removed (margins exposed and removed) to create the final epi-RSD structure with width larger than 1.3× fin pitch. This extraction of the sacrificial element enables the desired geometry while maintaining manufacturing yield
2Reliability
If epi-RSD width is increased to improve performance, then N-P space decreases, but trench silicide shorts may occur
Solution Approach 1:
The sacrificial liner acts as an intermediary structure that maintains separation between the epi-RSD and trench silicide during processing. It prevents direct contact that would cause shorts, while allowing the epi-RSD to achieve its full desired width for optimal performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by increasing the RSD width beyond the conventional limit, achieving a 1% nFET performance increase per 1 nm eSiP without yield penalties, and prevents shorts between RSD and trench silicide, thereby improving overall yield.
Implementation Method 1
forming a RSD region by EPI growth on each fin of the first group of fins
Data Source
AI summary
A method of forming a logic or memory cell with an epi-RSD width of larger than 1.3× fin pitch and the resulting device are provided. Embodiments include a device including a RSD region formed on each of a plurality of fins over a substrate, wherein the RSD has a width larger than 1.3× fin pitch, a TS formed on the RSD, and an ILD formed over the TS.