Epi Semiconductor Material Structures in Transistor Source/Drain Regions
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Solution Overview
Problem
In transistor devices on SOI substrates, the stress imparted by epitaxial semiconductor material in source/drain regions can relax during subsequent processing operations, reducing the performance characteristics of the transistors due to the lack of exposure of the underlying buried insulation layer during recess formation.
Innovation Solution
Forming recesses in the buried insulation layer under the active layer in the source/drain regions and depositing epitaxial semiconductor material within these recesses, allowing for a larger volume of stressed material to be positioned adjacent to the channel region, thereby reducing stress relaxation and maintaining desired performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If recesses are formed only in the active layer without exposing the buried insulation layer, then the recess formation process is simpler, but the stressed epi semiconductor material relaxes during subsequent processing operations, reducing transistor performance
Solution Approach 1:
The patent extends the recess formation from a two-dimensional surface modification into the third dimension by penetrating through the active layer to expose the buried insulation layer. This vertical dimensionality change creates deeper recesses that allow stressed epi semiconductor material to be positioned in a way that prevents stress relaxation during subsequent processing, thereby maintaining transistor performance while still using a relatively simple etching process.
2Reliability
If a larger volume of stressed epi semiconductor material is positioned adjacent the channel region, then stress relaxation is reduced and transistor performance is maintained, but the recess formation becomes more complex requiring exposure of the buried insulation layer
Solution Approach 1:
The patent segments the recess formation process into distinct stages: first forming openings in the active layer, then selectively etching the buried insulation layer in specific regions to create deeper recesses. This segmentation allows for precise control over where the stressed epi semiconductor material is positioned, enabling a larger volume of material to be placed adjacent the channel region without requiring a completely new or overly complex process flow.
3Ease of manufacture
If stressed epi semiconductor material is positioned only above the active layer, then the fabrication process is simpler, but stress relaxation occurs reducing the desired stress on the channel region
Solution Approach 1:
The patent implements a nested structure where the stressed epi semiconductor material is positioned both above and within recesses that extend into the buried insulation layer. This nesting arrangement allows the material to be embedded in a protective configuration that prevents stress relaxation during subsequent processing operations, maintaining the desired stress on the channel region while using standard fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains the desired stress on the channel region, enhancing transistor performance and reducing parasitic capacitance by positioning stressed epi semiconductor material both above and below the active layer, thus improving the reliability of the transistor devices.
Implementation Method 1
an epitaxial semiconductor material is grown on the active layer in the source/drain regions of the transistor device by performing an epitaxial growth process
Data Source
AI summary
One illustrative device disclosed herein includes a transistor formed above a semiconductor-on-insulator (SOI) substrate, wherein the transistor comprises a gate structure, a sidewall spacer and source/drain regions, openings formed in the active layer in the source/drain regions adjacent the sidewall spacer, recesses formed in a buried insulation layer of the SOI substrate in the source/drain regions of the transistor, wherein the recesses extend laterally under a portion of the active layer, and an epi semiconductor material positioned in at least the recesses in the buried insulation layer.