Epi-Silicon Buried Bit Lines for Vertical Pillar Transistors
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Solution Overview
Problem
Conventional semiconductor devices with vertical pillar transistors experience increased resistance in buried bit lines, leading to decreased current, increased RC delay, and deteriorated current driving capability due to ion-implanted N-type impurities.
Innovation Solution
The formation of buried bit lines using epi-silicon, with a conductive pattern of doped epi-silicon on portions between vertical pillar transistors, reduces resistance by growing epi-silicon in the silicon substrate to contact drain areas and arranging it along specific directions, accompanied by insulation layers and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ion implantation is used to form buried bit lines, then the manufacturing process is simple, but the current driving capability deteriorates
Solution Approach 1:
The patent modifies the manufacturing parameter from ion implantation to selective epitaxial growth. Although epitaxial growth is more complex than ion implantation, it provides superior electrical properties with lower resistance, thereby improving current driving capability. The process parameters are optimized to balance manufacturing complexity with performance requirements.
2Device complexity
If conventional ion-implanted buried bit lines are used, then the device structure is simple, but the RC delay increases
Solution Approach 1:
The patent changes the bit line formation parameter from ion implantation to selective epitaxial growth, which reduces resistance and thereby reduces RC delay. The increased process complexity is justified by the significant improvement in signal transmission speed and reduced timing delays.
Solution Approach 2:
The patent uses selective epitaxial growth to create precise epi-silicon regions that copy the desired bit line geometry with high fidelity. This copying approach ensures consistent dimensions and properties, leading to predictable and optimized electrical characteristics with reduced variability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces the resistance of buried bit lines compared to conventional methods, enhancing the characteristics and reliability of semiconductor devices with vertical pillar transistors.
Implementation Method 1
The buried bit lines are formed of epi-silicon
Implementation Method 2
The conductive pattern formed of the epi-silicon is doped with impurities
Data Source
AI summary
A semiconductor device comprises buried bit lines which are formed to be brought into contact with drain areas of vertical pillar transistors. The buried bit lines are arranged along a first direction in a silicon substrate. The buried bit lines are formed of epi-silicon to reduce the resistance of the buried bit lines.