Epi Source/Drain Lateral Spacing to Reduce Parasitic Capacitance
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Solution Overview
Problem
The parasitic gate-to-source/drain capacitance in transistor devices delays switching speed, becoming more problematic as device dimensions decrease, due to the physical configuration of transistors in integrated circuits.
Innovation Solution
A novel method involving the formation of a sacrificial sidewall spacer, an epi cavity, and selective deposition to create epi semiconductor material, followed by removal of sacrificial materials and formation of final sidewall spacers, which optimizes the positioning of epi material relative to the gate structure to reduce parasitic resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epi semiconductor material is formed in the source/drain regions adjacent the sidewall spacer, then the transistor structure is completed with conductive paths, but parasitic gate-to-S/D capacitance is created that delays switching speed
Solution Approach 1:
The patent introduces a lateral dimension separation by positioning the epi material further away from the gate structure through adjusted sidewall spacer formation. This increases the lateral distance between the gate and source/drain regions, reducing the parasitic capacitance coupling while maintaining vertical electrical connectivity for transistor function.
Solution Approach 2:
The sidewall spacer acts as an intermediary element that mediates the positioning between the gate structure and epi material. By controlling the spacer thickness and positioning, the patent creates an optimal separation distance that reduces parasitic capacitance while still allowing proper transistor operation through the source/drain regions.
2Productivity
If device dimensions continue to decrease, then integration density increases, but parasitic resistance and capacitance become more problematic
Solution Approach 1:
The patent applies local quality control by adjusting the sidewall spacer dimensions and epi material positioning specifically in the critical region near the gate structure. This localized optimization reduces parasitic effects at the gate-to-source/drain interface while maintaining compact overall device dimensions for high integration density.
Solution Approach 2:
By controlling the lateral positioning of epi material through sidewall spacer geometry, the patent manages parasitic effects in the lateral dimension while maintaining vertical stacking for compactness. This dimensional control allows smaller device footprints without proportionally increasing parasitic capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic resistance and capacitance, enhancing switching speed and performance in transistor devices by optimizing the placement and formation of epi source/drain material in integrated circuits.
Implementation Method 1
performing a selective deposition process to form a first sacrificial material selectively on at least the sacrificial sidewall spacer
Implementation Method 2
forming an epi semiconductor material in the epi cavity
Data Source
AI summary
One illustrative device disclosed herein includes an epi cavity formed in a semiconductor substrate adjacent a gate structure of a transistor and an epi semiconductor material comprising first and second portions. The first portion of the epi semiconductor material is positioned within the epi cavity. The second portion of the epi semiconductor material is positioned above the first portion of the epi semiconductor material and above a level corresponding to a level of an upper surface of the semiconductor substrate. The first portion of the epi semiconductor material has a first dimension in a direction corresponding to a gate length direction of the transistor and the second portion of the epi semiconductor material has a second dimension in a direction corresponding to the gate length direction of the transistor, wherein the first dimension is greater than the second dimension.