Epitaxial 3D NAND Memory Vertical Integration
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Solution Overview
Problem
Existing three-dimensional NAND strings have limitations in density and complexity due to the difficulty in forming active regions, which results in inefficient use of semiconductor material and time-consuming processes, and they typically provide only one bit per cell.
Innovation Solution
A monolithic three-dimensional NAND string is developed with memory cells stacked vertically, where each memory cell's active region is formed epitaxially on top of another, allowing for higher density and efficient integration of select transistors, enabling two bits per 4F2 area and allowing for multilevel cell operation with reduced processing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If repeated formation of sidewall spacers and etching of substrate is used to form active regions, then three-dimensional NAND string structure is achieved, but manufacturing complexity and processing time increase significantly
Solution Approach 1:
The patent divides the formation of active regions into separate epitaxial growth steps for each memory cell level. Instead of forming all active regions simultaneously through complex etching, the structure is built segmentally by sequentially growing semiconductor layers for individual cells, thereby simplifying the manufacturing process while achieving the three-dimensional stacked structure.
Solution Approach 2:
The patent transitions from planar active region formation to vertical stacking by growing semiconductor active regions in the vertical dimension through epitaxial processes. This dimensional change allows multiple active regions to be formed without requiring complex lateral etching and spacer formation, thus reducing manufacturing complexity while achieving three-dimensional integration.
2Device complexity
If conventional active region formation processes are used, then NAND string structure is created, but processing time becomes excessively long
Solution Approach 1:
The patent performs preliminary epitaxial growth of semiconductor layers before final patterning and device formation. By pre-forming the active regions through controlled epitaxial growth in the desired stacked configuration, subsequent processing steps are simplified and time-consuming repeated etching operations are eliminated, thereby reducing overall processing time while maintaining the complex NAND string structure.
3Quantity of substance
If vertical stacking of memory cells is implemented, then memory density increases, but formation of active regions becomes more difficult
Solution Approach 1:
The patent changes the formation parameters of active regions by using epitaxial growth conditions (temperature, pressure, gas flow, doping) specific to each memory cell level. This parameter control allows precise formation of vertically stacked active regions with appropriate electrical properties, making the high-density vertical structure manufacturable despite the complexity of forming multiple stacked cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory density, reduces processing time, and allows for high-performance binary operation with efficient use of semiconductor material, enabling vertical integration of select transistors and eliminating the need for extra space in the memory array.
Implementation Method 1
A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell
Implementation Method 2
a semiconductor active region of at least the first memory cell comprises recrystallized polysilicon
Data Source
AI summary
A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell. A semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell, such that a defined boundary exists between the semiconductor active region of the first memory cell and the semiconductor active region of the second memory cell.