Epitaxial Bridge Formation in 3D NAND Memory Arrays
Solution Overview
Problem
Current methods for forming arrays of memory cells, particularly in three-dimensional NAND architectures, face challenges in efficiently integrating vertical transistors and memory cells with effective control circuitry, leading to complexities in fabrication and performance.
Innovation Solution
The method involves a 'gate-last' or 'replacement-gate' processing approach, where a lower stack with alternating insulative and wordline tiers is formed, followed by epitaxial growth of bridges, and subsequent formation of an upper stack with interconnected channel openings, allowing for the integration of charge-blocking, charge-storage, and channel materials, along with control-gate formation to create elevationally-extending strings of transistors or memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional methods are used to form three-dimensional NAND memory arrays with vertically-stacked memory cells, then memory capacity and integration density are improved, but fabrication complexity and difficulty of integrating control circuitry increase
Solution Approach 1:
The fabrication process is divided into distinct sequential stages: forming lower stack with alternating insulative and wordline tiers, epitaxial growth of bridges, forming upper stack, and final gate formation. Each stage completes specific structural elements before proceeding to the next, breaking down the complex three-dimensional structure formation into manageable segments that reduce overall fabrication complexity
Solution Approach 2:
The lower stack and upper stack are formed in advance with their respective insulative and wordline tiers before the final gate structure is created. The bridges are epitaxially grown beforehand to establish the vertical pathways. These preliminary actions prepare the structural framework that simplifies the subsequent integration of control circuitry and memory cell formation
2Quantity of substance
If vertical transistors and memory cells are integrated in three-dimensional NAND architecture, then storage capacity is improved, but control over charge storage and passage becomes more difficult
Solution Approach 1:
Different regions of the vertical memory structure are assigned distinct functional properties: insulative tiers provide electrical isolation, wordline tiers provide control functionality, bridges provide charge passage pathways, and gates provide charge storage capability. This local differentiation of material properties and structural functions enables precise control over charge behavior at each location within the three-dimensional stack
Solution Approach 2:
The bridges serve as intermediary structures that connect the lower and upper stacks, providing controlled pathways for charge passage between them. The insulative tiers act as intermediaries that electrically isolate different functional regions. These intermediary elements enable precise control over charge storage and passage by mediating the interaction between different parts of the vertical structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient fabrication of vertically-stacked memory cells with improved integration of control circuitry, enhancing the performance and reliability of memory arrays by allowing for precise control over charge storage and passage, thereby addressing the complexities in three-dimensional memory cell integration.
Implementation Method 1
A bridge is epitaxially grown that covers individual of the lower channel openings
Data Source
AI summary
A method used in forming an array of elevationally-extending strings of memory cells comprises forming a lower stack comprising vertically-alternating insulative tiers and wordline tiers. Lower channel openings are in the lower stack. A bridge is epitaxially grown that covers individual of the lower channel openings. A lower void space is beneath individual of the bridges in the individual lower channel openings. An upper stack is formed above the lower stack. The upper stack comprises vertically-alternating insulative tiers and wordline tiers. Upper channel openings are formed into the upper stack to the individual bridges to form interconnected channel openings individually comprising one of the individual lower channel openings and individual of the upper channel openings. The interconnected channel openings individually have one of the individual bridges there-across. The individual bridges are penetrated through to uncover individual of the lower void spaces. Transistor channel material is formed in an upper portion of the interconnected channel openings elevationally along the vertically-alternating tiers in the upper stack.