Epitaxial Bridge Source/Drain Structure for Lower GAA Capacitance
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Solution Overview
Problem
Conventional gate-all-around (GAA) devices face challenges with bulk epitaxial source/drain (S/D) features that result in longer charging and discharging times and increased capacitance due to their size, degrading semiconductor device performance.
Innovation Solution
The formation of epitaxial S/D features as bridge-like layers between separated channel semiconductor layers, reducing their size and capacitance, and incorporating a bottom dielectric feature to minimize current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bulk epitaxial source/drain features are used in conventional GAA devices, then the device structure is simple to manufacture, but the charging and discharging time is long and capacitance is large
Solution Approach 1:
The bulk epitaxial source/drain feature is segmented into multiple thin epitaxial layers (first epitaxial layer, second epitaxial layer, third epitaxial layer) separated by dielectric layers. This segmentation reduces the effective thickness of conductive paths, thereby reducing capacitance and charging/discharging time while maintaining manufacturability through standard layer-by-layer fabrication processes.
Solution Approach 2:
The invention transitions from a three-dimensional bulk epitaxial structure to a multi-layered planar structure with dielectric separation. By introducing the vertical dimension of layering with intervening dielectric layers, the effective capacitance is reduced while the lateral footprint remains comparable, achieving faster switching without sacrificing manufacturing simplicity.
2Ease of manufacture
If bulk epitaxial source/drain features are used in conventional GAA devices, then the device structure is simple to manufacture, but the capacitance is relatively large
Solution Approach 1:
The bulk epitaxial source/drain feature is segmented into multiple thin epitaxial layers (first epitaxial layer, second epitaxial layer, third epitaxial layer) separated by dielectric layers. This segmentation reduces the effective thickness of conductive paths, thereby reducing capacitance and charging/discharging time while maintaining manufacturability through standard layer-by-layer fabrication processes.
Solution Approach 2:
Dielectric layers are introduced as intermediary structures between adjacent epitaxial layers. These dielectric layers act as electrical insulators that reduce parasitic capacitance between layers while allowing the structure to be manufactured using standard semiconductor fabrication processes, thus reducing overall capacitance without compromising ease of manufacture.
3Loss of time
If epitaxial layers are formed between separated channel semiconductor layers, then charging and discharging time is reduced and capacitance is reduced, but the device structure becomes more complex
Solution Approach 1:
The bulk epitaxial source/drain feature is segmented into multiple thin epitaxial layers (first epitaxial layer, second epitaxial layer, third epitaxial layer) separated by dielectric layers. This segmentation reduces the effective thickness of conductive paths, thereby reducing capacitance and charging/discharging time while maintaining manufacturability through standard layer-by-layer fabrication processes.
Solution Approach 2:
The structure employs a nested arrangement where dielectric layers are embedded between epitaxial layers, creating a compact multi-layered structure. This nesting approach achieves reduced capacitance and faster switching by minimizing parasitic effects while keeping the overall device footprint compact, thereby managing complexity through efficient spatial organization rather than increasing lateral dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the speed and performance of semiconductor devices by reducing charging and discharging times and capacitance, thereby improving overall device efficiency.
Implementation Method 1
epitaxial layers formed between the separated channel semiconductor layers
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.