Epitaxial Bridge Source/Drain Layout for Faster GAA Switching
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Solution Overview
Problem
Conventional gate-all-around (GAA) devices have bulk epitaxial source/drain features that result in longer charging and discharging times and higher capacitance due to their larger size, degrading the performance of semiconductor devices.
Innovation Solution
The epitaxial source/drain features are grown as smaller bridge layers between physically separated channel semiconductor layers, with S/D contacts formed to wrap each epitaxial layer and a bottom dielectric feature between the S/D contacts and the substrate to reduce current leakage, enhancing the speed and reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bulk epitaxial source/drain features are used in conventional GAA devices, then the device structure is simpler to manufacture, but the charging and discharging time increases and capacitance increases, degrading device performance
Solution Approach 1:
The bulk epitaxial source/drain feature is segmented into multiple separated epitaxial source/drain features. Each separated feature is formed between adjacent channel semiconductor layers, creating a segmented structure that reduces the volume of each individual epitaxial feature. This segmentation allows for faster charging and discharging times while maintaining manufacturability through controlled epitaxial growth processes.
Solution Approach 2:
The invention transitions from a three-dimensional bulk epitaxial feature to a more distributed configuration where separated epitaxial features are positioned in the vertical dimension between channel layers. This dimensional reorganization reduces the effective volume of each epitaxial feature while maintaining structural integrity and electrical functionality.
2Device complexity
If bulk epitaxial source/drain features are used in conventional GAA devices, then the manufacturing process is less complex, but the capacitance increases due to the larger size of the bulk feature
Solution Approach 1:
The bulk epitaxial source/drain is divided into multiple smaller separated epitaxial source/drain features. This segmentation reduces the total capacitance by distributing the charge storage across multiple smaller features rather than one large bulk feature, while the manufacturing complexity is managed through standardized epitaxial growth processes.
Solution Approach 2:
The invention changes the physical parameters of the epitaxial source/drain features by reducing their volume and distributing them spatially. This parameter change directly reduces capacitance while the manufacturing process complexity is controlled through precise control of epitaxial growth conditions and timing.
3Productivity
If smaller bridge epitaxial layers are grown between separated channel semiconductor layers, then the charging and discharging time is reduced and capacitance is decreased, but the manufacturing process becomes more complex
Solution Approach 1:
The separated epitaxial source/drain features are formed preliminarily between the channel semiconductor layers before final device assembly. This preliminary formation of the epitaxial features with controlled size and position enables faster device operation while the manufacturing complexity is managed by integrating the epitaxial growth into the existing semiconductor fabrication sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the charging and discharging time of the epitaxial features, decreases capacitance, and improves the overall performance of the semiconductor device by increasing speed and efficiency.
Implementation Method 1
epitaxial layers formed in a source/drain region between the first channel region and the second channel region, the epitaxial layers being separated from each other and each epitaxial layer being formed between the first portion and the second portion of each semiconductor layer
Data Source
AI summary
Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises semiconductor layers over a substrate, wherein the semiconductor layers are stacked up and separated from each other, each semiconductor layer includes a first portion in a first channel region of the substrate and a second portion in a second channel region of the substrate, epitaxial layers formed in a source/drain region between the first channel region and the second channel region, wherein the epitaxial layers are separated from each other and each epitaxial layer is formed between the first portion and the second portion of each semiconductor layer, and a conductive feature wrapping each of the epitaxial layers.