Recessed Epitaxial Semiconductor Structure for BSPDN Thinning Control
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices necessitates improved integration and electrical characteristics, particularly in the development of BackSide Power Delivery Network (BSPDN) structures with fine patterns and power rails on the backside of wafers, which current technologies struggle to achieve effectively.
Innovation Solution
A semiconductor device design featuring a substrate with recessed regions, epitaxially grown semiconductor regions of different conductivity types, and an epitaxial stopper layer, along with a dummy gate structure and protrusions, which enhances integration and electrical performance by controlling doping profiles and reducing thickness variations during backside thinning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to achieve high performance and high speed, then functionality and processing power are improved, but manufacturing precision and pattern control become more difficult
Solution Approach 1:
The patent transitions from planar transistor structures to vertical three-dimensional structures by forming recessed regions and stacking semiconductor layers vertically. This dimensional change allows multiple transistor channels to be packed into a smaller footprint area, increasing integration density while maintaining controllable manufacturing processes through sequential layer formation.
Solution Approach 2:
The patent divides the substrate into multiple recessed regions with alternating conductivity types (N-type and P-type), creating segmented functional zones. This segmentation enables independent optimization of different device regions and allows for precise control of doping profiles in each segment, maintaining manufacturing precision while achieving high integration.
2Productivity
If BSPDN structure with power rails on backside is implemented to improve integration, then device density is increased, but substrate thickness control and uniformity become more challenging
Solution Approach 1:
The patent forms the recessed regions and semiconductor layers on the front surface of the substrate before performing backside thinning. This preliminary structuring establishes a mechanical stop that prevents excessive thinning and ensures uniform thickness control during the backside processing, enabling BSPDN implementation while maintaining substrate integrity.
Solution Approach 2:
The recessed regions with alternating conductivity types serve as intermediary structures that mediate between the front surface device structures and the backside power rails. These regions provide mechanical support and electrical isolation, enabling thinning to the backside while maintaining uniform thickness and preventing substrate damage.
3Productivity
If fine patterns are implemented to increase integration, then device capacity is improved, but doping profile control and electrical characteristics deteriorate
Solution Approach 1:
The patent applies different doping profiles and conductivity types to specific local regions (alternating N-type and P-type recessed regions) rather than uniform doping throughout. This local quality approach allows optimization of electrical characteristics in each region while maintaining fine pattern structures, preventing degradation of device performance despite increased integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves integration and electrical characteristics by allowing for precise control of doping profiles and reduced substrate thickness variations, enabling efficient power delivery and enhanced performance in semiconductor devices.
Implementation Method 1
Each of the first to third semiconductor regions is formed of an epitaxial layer
Data Source
AI summary
A semiconductor device includes a substrate having a recessed region, a first semiconductor region including a first semiconductor layer on a bottom surface and an inner side surface of the recessed region and a first protrusion on the first semiconductor layer, and having a first conductivity type, a second semiconductor region including a second semiconductor layer on the first semiconductor layer and a second protrusion on the second semiconductor layer, and having a second conductivity type, a third semiconductor region including a third semiconductor layer on the second semiconductor layer and a third protrusion on the third semiconductor layer, and having the first conductivity type, a epitaxial stopper layer covering the bottom surface of the recessed region between the first semiconductor region and the substrate and including a material different from materials of the first semiconductor region, and a dummy gate structure intersecting the first to third protrusions on the substrate.