Epitaxial Cap Layer Fabrication for MOS Device Performance Consistency
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Solution Overview
Problem
As semiconductor devices shrink, the reduced channel length in MOS transistors leads to non-uniform silicon germanium epitaxy growth, causing performance mismatches due to varying thickness and mechanical stress, which affects electron and hole mobility and device performance.
Innovation Solution
A method for fabricating MOS devices involving two epitaxy growth processes with controlled temperatures and dopant concentrations, forming semiconductor compound layers with a nonsilicon element, and a cap layer with a specific included angle and facet, to enhance turn-on currents and reduce turn-off currents, thereby improving performance consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon germanium epitaxy is used to apply compressive stress to enhance hole mobility, then device performance is improved, but non-uniform growth due to loading effects causes thickness variations and performance mismatches
Solution Approach 1:
The source/drain structure is divided into three distinct segments: a first semiconductor compound layer (SiGe) for applying compressive stress, a buffer layer for stress isolation, and a second semiconductor compound layer (SiC) for protection and mobility enhancement. This segmentation allows each layer to perform its specific function independently, resolving the contradiction between achieving uniform stress distribution and maintaining thickness control.
Solution Approach 2:
A buffer layer is introduced as an intermediary between the first semiconductor compound layer (SiGe) and the second semiconductor compound layer (SiC). This buffer layer mediates the mechanical stress from the SiGe layer, preventing direct transmission that would cause non-uniform growth in the SiC layer, while still allowing the SiGe layer to effectively stress the channel for enhanced hole mobility.
2Speed
If the channel length is reduced to increase operating speed, then transistor speed is improved, but mechanical stress application becomes less effective
Solution Approach 1:
The invention changes the material parameters of the source/drain structure by using a composite of three layers with different material properties (SiGe, buffer, and SiC). This parameter change allows effective mechanical stress application even in shortened channel lengths, as the layered structure provides more controlled and distributed stress compared to a single-material approach.
3Reliability
If germanium content is increased to enhance hole mobility, then carrier mobility is improved, but epitaxial growth uniformity deteriorates due to loading effects
Solution Approach 1:
The high-germanium-content layer is segmented into the first semiconductor compound layer, which is separated from the second semiconductor compound layer by a buffer layer. This segmentation allows the high germanium content layer to effectively stress the channel for enhanced hole mobility, while the buffer layer prevents the loading effects from propagating to the second layer, maintaining its growth uniformity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances turn-on currents, reduces turn-off currents, and improves device performance consistency by mitigating the effects of non-uniform growth and mechanical stress, resulting in at least 6% improvement in performance matching.
Implementation Method 1
A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers.
Data Source
AI summary
A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.