Epitaxial Channel Barrier Layer for FinFET Dopant Control
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Solution Overview
Problem
The complexity and cost of fabricating FinFET transistors have increased due to process complexity, necessitating improved manufacturing methods for semiconductor devices.
Innovation Solution
A method involving the formation of a barrier layer between the channel and well in semiconductor devices, using silicon oxide or silicon carbide, to reduce dopant migration and improve transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET transistors are used to increase functional density, then production efficiency and cost are improved, but process complexity increases
Solution Approach 1:
The patent segments the channel region into multiple portions with different doping concentrations. The channel is divided into a first channel portion with a first doping concentration and a second channel portion with a second doping concentration, allowing independent optimization of different regions to reduce overall process complexity while maintaining high functional density
Solution Approach 2:
The patent applies local quality by creating non-uniform doping distribution within the channel. Different regions of the channel have different doping concentrations tailored to specific functional requirements, enabling optimized transistor performance without requiring complex FinFET structures throughout the entire device
2Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the doping concentration parameter across different channel regions rather than relying solely on geometric scaling. By adjusting doping concentrations (first doping concentration vs. second doping concentration) instead of only reducing dimensions, the patent achieves enhanced functionality while maintaining manufacturability at standard geometry sizes
3Reliability
If dopant migration is reduced to improve transistor performance, then reliability is improved, but additional processing steps are required
Solution Approach 1:
The patent performs preliminary doping during the channel formation step itself, rather than requiring separate post-formation doping steps. The channel portions are doped with appropriate concentrations during their creation, preventing dopant migration issues before they can occur and eliminating the need for additional complex processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The barrier layer reduces dopant migration, enhances drain induced barrier lowering (DIBL), improves effective drain current (Ideff) and source off current (Isoff), and optimizes consumed active power (W) and frequency (f) of transistors.
Implementation Method 1
forming a barrier layer between the channel and well, the barrier layer including at least one of either silicon carbon or silicon oxide
Data Source
AI summary
A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.