Epitaxial Channel Layer for MOSFET Threshold Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The scaling down of MOSFET devices to reduce gate length leads to loss of gate electrode control, resulting in threshold voltage roll-off and instability due to non-uniform dopant distribution from threshold adjustment ion implantation, making it difficult to control minimum voltage and device leakage.

Innovation Solution

A semiconductor transistor design featuring an epitaxial channel layer of P-type doped silicon or silicon germanium grown between source and drain regions, with a shallow trench isolation region and a gate dielectric layer, replacing the threshold adjustment ion implantation process to achieve uniform dopant concentration and improved carrier mobility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If threshold adjustment ion implantation is used to control threshold voltage, then gate electrode control is improved, but dopant distribution becomes non-uniform causing minimum voltage instability and device leakage

Engineering Contradiction:
Improvegate electrode controlVSAvoiddopant distribution uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent changes the fundamental parameter of dopant introduction from ion implantation to in-situ doping during epitaxial growth. This parameter change enables uniform dopant distribution throughout the channel layer while maintaining effective threshold voltage control, resolving the contradiction between gate control and dopant uniformity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical ion implantation process with a chemical epitaxial growth process that incorporates dopants in-situ. This substitution eliminates the Gaussian distribution problem inherent in ion implantation while achieving uniform dopant concentration, thereby resolving the manufacturing precision issue.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If gate length is reduced to increase device speed, then productivity is improved, but gate electrode control is lost causing threshold voltage roll-off

Engineering Contradiction:
Improvedevice speedVSAvoidthreshold voltage stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the channel formation method to epitaxial growth with in-situ doping, which maintains effective gate control even at reduced gate lengths. This parameter change allows continued scaling for higher productivity while preserving threshold voltage stability through uniform dopant distribution and improved gate authority.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The epitaxial channel layer provides uniform dopant distribution, stabilizing the minimum voltage and reducing device leakage, while enhancing carrier mobility and control over the channel region.

Implementation Method 1

an epitaxial channel layer of the first conductivity type grown from the main surface of the substrate and disposed between the source region and the drain region

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS11637183B2Method of forming a semiconductor transistor having an epitaxial channel layer
Publication Date: 2023.04.25 UNITED SEMICONDUCTOR (XIAMEN) CO LTD
  • US11637183B2 patent drawing
  • US11637183B2 patent drawing
  • US11637183B2 patent drawing

AI summary

A method for fabricating a semiconductor transistor is disclosed. A substrate of a first conductivity type is provided. An ion well of a second conductivity type is formed in the substrate. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate. A gate dielectric layer is formed on the epitaxial channel layer. A gate is formed on the gate dielectric layer. A source region and a drain region are then formed in the substrate. The source region and the drain region have the first conductivity type.