Epitaxial Channel Strain Confinement in Semiconductor Fabrication
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Solution Overview
Problem
The fabrication of semiconductor devices with extremely small feature sizes faces challenges due to plastic strain relaxation in bulk epitaxial material, which reduces the lattice constant mismatch and strain in the crystalline substrate, limiting the performance of transistors.
Innovation Solution
The method involves forming epitaxial channels in the substrate with a hardmask overlying the substrate, creating openings for epitaxial material deposition, and confining the epitaxial material within these channels to maintain strain, allowing for the fabrication of transistors with extremely small channel lengths without high-precision alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Force
If large area epitaxial deposition is used to induce strain in the substrate, then strain can be created in the crystalline substrate, but plastic strain relaxation occurs in the bulk epitaxial material which reduces the lattice constant mismatch and strain imparted to the substrate
Solution Approach 1:
The patent divides the epitaxial material into discrete regions or channels rather than using large area bulk epitaxial deposition. This segmentation prevents plastic strain relaxation by limiting the epitaxial material to confined channels where the strain can be maintained without relaxation, thereby preserving the lattice constant mismatch and the strain imparted to the substrate.
Solution Approach 2:
The patent applies epitaxial material locally in specific channels rather than uniformly across large areas. This local quality approach ensures that strain is induced precisely where needed in the active device regions while avoiding the plastic strain relaxation that occurs in bulk epitaxial material, maintaining optimal lattice constant mismatch for carrier mobility enhancement.
2Force
If hetero-epitaxial processes are used to form materials with different lattice constants, then strain can be induced in the substrate, but the process produces large regions of epitaxial material that limit the fabrication of devices with feature sizes less than 45 nm
Solution Approach 1:
The patent segments the epitaxial material into narrow channels with dimensions suitable for small feature size devices. By confining the epitaxial material to these channels rather than using large area deposition, the process enables fabrication of devices with feature sizes considerably less than 45 nm while maintaining the necessary strain in the substrate.
Solution Approach 2:
The patent transitions from two-dimensional large area epitaxial deposition to a more confined, channel-based structure that effectively reduces the dimensional footprint. This dimensional change allows the epitaxial material to be placed precisely where needed for small feature size devices without the constraints of large area deposition processes.
3Length of moving object
If advanced transistor materials and hetero-epitaxial substrate regions are used, then MOS devices with gate lengths on the order of 45 nm can be fabricated, but plastic strain relaxation in bulk epitaxial material reduces the strain and limits performance improvement
Solution Approach 1:
The patent segments the epitaxial material into discrete channels that are integrated with advanced transistor structures having gate lengths on the order of 45 nm. This segmentation prevents plastic strain relaxation while maintaining compatibility with small gate length devices, thereby preserving the strain necessary for performance improvement.
Solution Approach 2:
The patent changes the geometric parameters of the epitaxial material from large area bulk structures to narrow channels with dimensions optimized for small gate length devices. This parameter change enables the simultaneous achievement of small gate lengths (45 nm and below) and maintained strain through prevention of plastic strain relaxation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively induces and maintains strain in the substrate, enabling the production of highly integrated transistors with improved carrier mobility and performance, even at small feature sizes, by limiting plastic strain relaxation and optimizing lattice mismatch.
Implementation Method 1
strain can be induced in devices formed in a single crystal silicon substrate by forming regions of silicon germanium (SiGe) or silicon carbide (SiC). Since the lattice constant of SiGe is larger than that of silicon, the lattice mismatch puts the silicon under tension and the charge carrier mobility increases through the strained silicon lattice.
Implementation Method 2
hetero-epitaxial processes can be used to form a wide range of materials, such as germanium (Ge) and silicon (Si) in III-IV substrates
Data Source
AI summary
A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.