Low-Temperature Epitaxial Contact Formation for Semiconductor Devices
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Solution Overview
Problem
Conventional methods for fabricating contacts for p-type and n-type field effect transistors (FETs) on a common substrate face challenges such as contact damage from reactive-ion etching, polymer residue, and increased contact resistance due to silicon nitride traces, making it difficult to maintain low contact resistance between metallic contacts and semiconductor material.
Innovation Solution
A method involving low-temperature epitaxial deposition of semiconductor material layers, implantation of elements to form amorphous layers, and subsequent annealing to create metastable alloy layers, followed by metal liner deposition and annealing to form metal-semiconductor compounds, which reduces contact resistance and improves the surface condition of the trench.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If reactive-ion etching (RIE) process is used during contact fabrication, then contact trenches can be formed, but contact damage occurs and polymer residue is left at the bottom of the contact trench
Solution Approach 1:
The patent changes the etching parameters by switching from RIE to a different etching process that reduces or eliminates polymer residue deposition. This parameter change in the etching process allows contact trench formation while avoiding the harmful side effects of contact damage and polymer residue accumulation at the trench bottom.
Solution Approach 2:
The patent introduces an intermediary cleaning step or process modification that acts as a mediator between the etching process and the final contact structure. This intermediary action removes polymer residue and prevents contact damage without compromising the trench formation quality.
2Ease of manufacture
If conventional contact fabrication methods are used, then contact trenches can be formed, but traces of silicon nitride remain in the trench causing increased contact resistance
Solution Approach 1:
The patent extracts or removes the harmful silicon nitride traces from the contact trench through a specific cleaning step or process modification. This extraction eliminates the source of increased contact resistance while preserving the trench structure formed by the etching process.
Solution Approach 2:
The patent modifies the etching or cleaning process parameters to selectively remove silicon nitride traces from the trench bottom. By changing these parameters, the process achieves complete removal of contaminating residues that would otherwise increase contact resistance between the metal contact and semiconductor material.
3Ease of manufacture
If conventional contact fabrication methods are used, then contact trenches can be formed, but gouging of the source-drain epitaxial layer occurs encroaching upon the fin structure
Solution Approach 1:
The patent applies a protective layer or modifies the etching process beforehand to cushion or protect the source-drain epitaxial layer during contact trench formation. This prior protection prevents gouging and encroachment on the fin structure while still allowing the contact trench to be formed through the inter-level dielectric layer.
Solution Approach 2:
The patent changes the etching process parameters (such as etch rate, selectivity, or power settings) to achieve more precise control over the contact trench formation. This parameter optimization prevents excessive etching that would cause gouging of the source-drain epitaxial layer and encroachment on the fin structure, thereby maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of p-type and n-type FETs on a common substrate with low contact resistance, enhancing the performance and reliability of semiconductor devices by minimizing contact damage and residue issues.
Implementation Method 1
depositing a semiconductor material layer on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device... through low-temperature epitaxial deposition
Implementation Method 2
annealing the amorphous layer to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region
Implementation Method 3
depositing at least one metal liner layer upon the p-type source drain region and the n-type source/drain region
Data Source
AI summary
A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.