Integrated Circuit ESD Protection via Stacked Epitaxial Diodes

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Solution Overview

Problem

As semiconductor integrated circuits (ICs) scale down, they become increasingly susceptible to electrostatic discharge (ESD) damage, necessitating effective ESD protection mechanisms to prevent device failure.

Innovation Solution

The integration of diode structures within the ICs, specifically designed to form PIN or PN junctions using doped epitaxial features, which are strategically positioned to provide efficient ESD protection through a combination of diodes and ESD power-clamp circuits, including RC-invertors and BigFETs, to create low-resistance paths during ESD events.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device dimensions are scaled down to increase functional density, then production efficiency and cost are improved, but susceptibility to ESD damage increases

Engineering Contradiction:

Improveproduction efficiencyVSAvoidESD damage susceptibility

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The ESD protection circuit is segmented into multiple discrete components including diodes, RC-invertors, and BigFETs, each positioned at specific locations within the IC to provide distributed protection against ESD damage while maintaining scaled-down device dimensions

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Diode structures are introduced as intermediary protection elements between external interfaces and internal circuits, providing a controlled path for ESD current to bypass sensitive internal circuitry while allowing normal signal operation

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If ESD protection circuits are added to protect against ESD damage, then device reliability is improved, but device complexity increases

Engineering Contradiction:

ImproveESD protection capabilityVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The ESD protection circuit employs universal protection mechanisms that handle multiple ESD stress conditions (different polarities, voltage levels, and pulse durations) through a unified architecture of diodes, RC-invertors, and BigFETs, preventing the need for separate protection circuits for each ESD scenario

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent utilizes three-dimensional vertical structures including deep trench isolation features and vertically stacked diode configurations to provide ESD protection without increasing planar footprint, effectively adding a vertical dimension to the protection architecture

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11569223B2Integrated circuit and method for fabricating the same

Publication Date: 2023.01.31 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method for fabricating an integrated circuit is provided. The method includes etching a first recess in a semiconductor structure; forming a first doped epitaxial feature in the first recess; and forming a second doped epitaxial feature over the first doped epitaxial feature, wherein the second doped epitaxial feature has a conductive type opposite to a conductive type of the first doped epitaxial feature.