Epitaxial Dislocation Confinement in Semiconductor Fin Structures
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Solution Overview
Problem
Current stress-memorization techniques for semiconductor manufacturing require multiple costly photolithography operations and result in dislocations extending into the original substrate, affecting device performance.
Innovation Solution
A method that directly forms a recess in the source/drain region and grows a secondary epitaxial region within it, in situ forming dislocations that do not extend to the original substrate, eliminating the need for capping layer formation, pre-amorphization implantation, thermal anneal, and capping layer removal steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stress-memorization techniques are applied to improve device performance, then charge mobility is enhanced, but dislocations extend into the original substrate affecting device performance
Solution Approach 1:
The invention segments the semiconductor structure by introducing a distinct third semiconductor layer between the substrate and the regrown source/drain region. This layer acts as a barrier that confines dislocations within the source/drain region while preventing their extension into the substrate, thus maintaining device performance while enabling stress memorization benefits
2Reliability
If multiple photolithography operations are used for stress-memorization techniques, then strained material is achieved, but manufacturing cost increases
Solution Approach 1:
The invention performs preliminary action by forming the third semiconductor layer and the recess structure before the regrowth process. This pre-configuration allows the stress memorization to be achieved through a simplified single photolithography operation followed by selective epitaxial regrowth, eliminating the need for multiple photolithography steps while maintaining strained material quality
3Reliability
If multiple processing steps are used for stress-memorization, then strained material is formed, but manufacturing efficiency decreases
Solution Approach 1:
The third semiconductor layer is formed in advance with appropriate lattice mismatch characteristics, and the recess is pre-formed to the required depth. This preliminary preparation enables the subsequent regrowth step to complete the stress memorization process in a single operation, significantly improving manufacturing efficiency while maintaining the quality of strained material
Solution Approach 2:
The invention utilizes parameter changes in the lattice constant of the third semiconductor layer relative to both the substrate and the source/drain region. By carefully selecting materials with specific lattice constants, the system achieves automatic dislocation confinement during the regrowth process, eliminating the need for multiple processing steps and thermal annealing operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge mobility and device performance by maintaining dislocations only in the source/drain regions, improving manufacturing efficiency and reducing costs by eliminating unnecessary steps.
Implementation Method 1
forming a second semiconductor layer having a second lattice constant in the recess, wherein at least one dislocation is in-situ formed in the second semiconductor layer
Data Source
AI summary
The present disclosure provides a semiconductor structure having an insulating layer positioning on a substrate; a semiconductor fin partially located in the insulating layer; and a metal gate over the semiconductor fin and the insulating layer. The semiconductor fin includes a first region including a first lattice constant and a second region in proximity to the metal gate, including a second lattice constant. At least one dislocation is located only in the second region of the semiconductor fin. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a gate over a first semiconductor layer, removing a portion of the first semiconductor layer in proximity to a sidewall of the gate and obtaining a recess, and forming a second semiconductor layer in the recess. At least one dislocation is in-situ formed in the second semiconductor layer without extending to the first semiconductor layer.