Epitaxial Silicon Emitter Planarization for BJT Contact Resistance
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Solution Overview
Problem
The formation of emitter regions in bipolar junction transistors (BJTs) at reduced scales faces challenges due to non-planar upper surfaces and faceted sidewalls, leading to increased contact resistance and reduced BJT performance, as the silicide layer formation is limited by thicker silicon deposition around faceted sidewalls.
Innovation Solution
A cyclic growth-etching procedure is employed to form the emitter layer, combining non-selective deposition and etching phases to maintain desired epitaxial crystal structure and achieve planarity, thereby increasing the contact area and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial growth method is used to form emitter region, then desirable electrical properties are obtained, but non-planar upper surface and faceted sidewalls are formed leading to increased contact resistance
Solution Approach 1:
The patent applies periodic action by implementing cyclic iterations between selective epitaxial growth and planarization steps. The process repeatedly grows silicon layers to achieve desired electrical properties, then performs planarization to restore surface flatness, and repeats this cycle multiple times. This periodic alternation between growth and planarization resolves the contradiction by maintaining both desirable electrical properties and surface planarity throughout the emitter region formation process.
Solution Approach 2:
The patent segments the emitter region formation into multiple discrete cycles, where each cycle consists of a growth phase followed by a planarization phase. Instead of forming the entire emitter region in a single continuous growth step, the process divides it into sequential segments that can be independently controlled and optimized, allowing simultaneous achievement of electrical performance and surface quality.
2Reliability
If silicide layer is formed to reduce contact resistance, then contact resistance decreases, but thicker silicon deposition around faceted sidewalls limits effective silicide formation area
Solution Approach 1:
The patent applies preliminary action by performing planarization of the emitter region upper surface before forming the silicide layer. This preliminary planarization step removes the faceted sidewalls and non-planar features that would otherwise limit the effective contact area. By preparing a flat surface in advance, the subsequent silicide layer can be formed uniformly across the entire intended contact area, maximizing the effective contact area and minimizing contact resistance.
3Productivity
If emitter region is formed at reduced scales, then device scaling is achieved, but non-planar surface features become more pronounced increasing contact resistance
Solution Approach 1:
The patent applies continuity of useful action by maintaining continuous cyclic iterations of growth and planarization throughout the emitter region formation process at reduced scales. The process continuously alternates between adding silicon material to achieve scaling and removing non-planar features to maintain low contact resistance. This continuous cyclic action ensures that even at reduced device scales, the emitter region maintains both the desired dimensions and the surface planarity required for low contact resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a BJT with reduced contact resistance and improved performance by enhancing the planarity of the emitter layer, allowing for a larger effective contact area between the emitter layer and overlying features.
Implementation Method 1
growing, in a chamber, an epitaxial silicon-rich layer having a first sidewall adjacent to the gate structures and a first central portion
Implementation Method 2
shaping the epitaxial silicon-rich layer to form a second sidewall adjacent to the gate structures and a second central portion, wherein a first height difference between the first sidewall and the first central portion is greater than a second height difference between the second sidewall and the second central portion
Data Source
AI summary
A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate including a first semiconductive region of a first conductive type and gate structures over the first semiconductive region, wherein a gap between the gate structures exposes a portion of the first semiconductive region; and forming a second semiconductive region of a second conductive type in the gap starting from the exposed portion of the first semiconductive region. The forming of the second semiconductive region includes: growing, in a chamber, an epitaxial silicon-rich layer having a first sidewall adjacent to the gate structures and a first central portion; and, in the chamber, shaping the epitaxial silicon-rich layer to form a second sidewall adjacent to the gate structures and a second central portion, wherein a first height difference between the first sidewall and the first central portion is greater than a second height difference between the second sidewall and the second central portion.