Self-Aligned Epitaxial Etch Stop for FinFET Yield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuit manufacturing, the use of fin-type transistors faces challenges with epitaxial growth when the dummy gate pitch is too small, leading to degraded growth and damage during the removal of hardmasks and liners, which increases processing steps and reduces yield.
Innovation Solution
The method avoids forming conventional liners for epitaxial growth, instead using self-aligned epitaxial source/drain regions and etch stop layers formed through decoupled plasma processing, converting the cap layer into a nitride/oxide etch stop layer without damaging the epitaxial layers, and positioning the etch stop layers only on source/drain regions to minimize damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional liners are formed for epitaxial growth, then epitaxial source/drain regions can be grown, but processing steps increase and yield decreases due to damage during hardmask and liner removal
Solution Approach 1:
The patent removes the conventional liner layer from the process flow. Instead of forming a liner before epitaxial growth, the method directly grows self-aligned epitaxial source/drain regions on the substrate, eliminating the liner formation and removal steps that cause damage and reduce yield.
Solution Approach 2:
The patent performs preliminary self-aligned epitaxial growth of source/drain regions before forming the gate structure. This preliminary action establishes the source/drain regions with precise alignment to the gate, eliminating the need for subsequent liner removal that would damage these regions.
2Reliability
If decoupled plasma processing is used to convert cap layer to etch stop layer, then damage to epitaxial layers is minimized, but processing time increases
Solution Approach 1:
The patent uses decoupled plasma processing to change the chemical composition of the cap layer, converting it from silicon to silicon nitride or silicon oxide. This parameter change creates an etch stop layer with different etch selectivity, protecting the underlying epitaxial regions during subsequent processing while using controlled plasma parameters to minimize damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces processing complexity, minimizes damage to epitaxial layers, and enhances yield by eliminating the need for additional masking and liner layers, while ensuring precise alignment and protection of the etch stop layers.
Implementation Method 1
convert the cap layer into a nitride/oxide etch stop layer in a decoupled plasma process
Implementation Method 2
convert the cap layer into a nitride/oxide etch stop layer in a decoupled plasma process
Implementation Method 3
remove the spacer layer in an anisotropic etching process that removes material from horizontal surfaces at a much higher rate than from vertical surfaces
Implementation Method 4
epitaxially grow first source/drain structures on the area of the first layer laterally adjacent the first gate structure, and epitaxially grow a first cap layer on the first source/drain structures
Data Source
AI summary
Methods form an integrated circuit structure that includes complementary transistors on a first layer. An isolation structure is between the complementary transistors. Each of the complementary transistors includes source/drain regions and a gate conductor between the source/drain regions, and insulating spacers are between the gate conductor and the source/drain regions in each of the complementary transistors. With these methods and structures, an etch stop layer is formed only on the source/drain regions.