Epitaxial Extension CMOS Transistor Resistance Control
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Solution Overview
Problem
The scaling of semiconductor devices makes it difficult to control the resistance of source and drain extension regions in MOSFETs, leading to increased statistical variation and performance degradation due to the ion scattering effect during conventional ion implantation, which affects the on-current and switching speed.
Innovation Solution
A method involving the formation of horizontal-step-including trenches in a semiconductor layer, where a pair of first trenches are formed to a first depth around a gate structure, followed by the creation of a disposable spacer and a pair of second trenches to a greater second depth, allowing for selective epitaxy to form integrated epitaxial source and drain extension regions, thereby reducing resistance and mitigating the short channel effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional ion implantation is used to dope source and drain extension regions, then the doping process is simple, but the resistance control becomes difficult and statistical variation increases due to ion scattering effects
Solution Approach 1:
The patent replaces the mechanical ion implantation process with a chemical epitaxial growth process. Instead of physically implanting dopant ions into the semiconductor lattice, dopants are incorporated during selective epitaxial growth of source and drain regions, enabling precise resistance control through chemical reaction kinetics rather than mechanical bombardment
Solution Approach 2:
The patent changes the fundamental parameter of dopant introduction from post-growth ion implantation to in-situ dopant incorporation during epitaxial growth. This allows continuous control of dopant concentration through growth conditions (temperature, pressure, gas flow) rather than discrete ion implantation doses, reducing statistical variation
2Ease of manufacture
If ion implantation is used to dope source and drain extension regions, then the process is straightforward, but short channel effect performance degrades due to dopant interdiffusion at interfaces
Solution Approach 1:
The patent replaces ion implantation with selective epitaxial growth, where dopants are incorporated during the growth process rather than implanted afterward. This eliminates the mechanical bombardment that causes dopant redistribution and interdiffusion at interfaces, maintaining sharp dopant profiles and reducing short channel effects
Solution Approach 2:
The patent performs dopant incorporation during the epitaxial growth process itself, before subsequent processing steps. This preliminary incorporation of dopants during growth ensures precise spatial control and prevents later dopant migration that would occur with post-growth ion implantation
3Area of moving object
If source and drain regions are reduced in lateral dimensions for scaling, then device density increases, but resistance control becomes more difficult due to statistical variation
Solution Approach 1:
The patent changes from discrete ion implantation dosing to continuous epitaxial growth parameters for dopant incorporation. This allows precise control of dopant concentration even in highly scaled regions by adjusting growth conditions, reducing statistical variation that plagues ion implantation in sub-100nm devices
Solution Approach 2:
The patent replaces the statistical nature of ion implantation with the deterministic chemical process of epitaxial growth. In scaled devices where ion scattering causes significant variation, the chemical incorporation of dopants during growth provides more predictable and controllable resistance characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the control over the resistance of source and drain extension regions, improving the performance of MOSFETs by reducing statistical variation and minimizing the short channel effect, resulting in better on-current and switching speed.
Implementation Method 1
selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region
Data Source
AI summary
A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over epitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.