Epitaxial Ferroelectric Memory Elements in 3D NAND
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in integrating efficient ferroelectric memory elements and manufacturing methods that effectively utilize epitaxial and textured ferroelectric materials within a monolithic three-dimensional NAND string structure.
Innovation Solution
A method involving the formation of an alternating stack of insulating and sacrificial material layers over a substrate, followed by the creation of vertical semiconductor channels and ferroelectric dielectric layers, with electrically conductive layers formed in the backside recesses, enabling the construction of a three-dimensional memory device with epitaxial ferroelectric memory elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional three-dimensional memory devices are used, then manufacturing simplicity is maintained, but storage capacity and performance are limited
Solution Approach 1:
The patent implements a nested structure where vertical semiconductor channels are surrounded by ferroelectric dielectric layers, which are in turn surrounded by electrically conductive layers forming a three-dimensional NAND string architecture. This nested arrangement maximizes storage capacity within the available device volume by utilizing multiple concentric layers for data storage.
Solution Approach 2:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertical NAND strings by stacking alternating layers of insulating and electrically conductive materials vertically. This dimensional change enables significantly higher storage capacity by utilizing the vertical dimension for multiple storage layers.
2Reliability
If epitaxial ferroelectric materials are integrated, then ferroelectric memory element efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the vertical semiconductor channels and alternating insulating and sacrificial material layers before integrating the epitaxial ferroelectric materials. This sequence prepares the structural framework in advance, facilitating subsequent ferroelectric layer deposition and reducing overall manufacturing complexity.
Solution Approach 2:
The patent uses sacrificial material layers as intermediaries during the manufacturing process. These sacrificial layers are deposited between the insulating layers, allow for controlled formation of backside recesses, and are subsequently removed to create the final three-dimensional NAND string structure, simplifying the integration of epitaxial ferroelectric materials.
3Quantity of substance
If vertical semiconductor channels with ferroelectric dielectric layers are formed, then storage density is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the memory device into distinct functional layers: insulating layers, sacrificial material layers, vertical semiconductor channels, ferroelectric dielectric layers, and electrically conductive layers. This segmentation allows each layer to be formed and optimized independently, reducing the cumulative precision requirements while achieving high storage density through the stacked architecture.
Solution Approach 2:
The sacrificial material layers serve as intermediaries that simplify the formation of backside recesses. By depositing and subsequently removing these sacrificial layers, the patent creates precise recess structures without requiring direct high-precision machining, thereby reducing manufacturing precision requirements while maintaining high storage density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the development of high-density, efficient three-dimensional memory devices with improved ferroelectric memory elements, enhancing storage capacity and performance by leveraging epitaxial and textured ferroelectric layers within a monolithic NAND string structure.
Implementation Method 1
forming vertical stacks of single crystalline ferroelectric dielectric layers, wherein each vertical stack of single crystalline ferroelectric dielectric layers is formed adjacent to a respective one of the vertical semiconductor channels
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel, a vertical stack of majority germanium layers each containing at least 51 atomic percent germanium, and a vertical stack of ferroelectric dielectric layers.