Epitaxial Fin Structure With Inner Spacer Air Gap for Lower Capacitance
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming reliable devices at increasingly smaller sizes, where feature sizes continue to decrease, making fabrication processes more difficult and complex, and it is hard to control the growth of epitaxial structures to reduce parasitic capacitance and improve electrical performance.
Innovation Solution
The solution involves forming a semiconductor structure with fins where an epitaxial structure is grown on the fins, with a dielectric material forming an inner spacer structure between the fins and outer spacers on either side, where the top surface of the inner spacer is below the outer spacers, confining lateral growth and reducing parasitic capacitance by creating an air gap and optimizing the thickness of the spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity increases and reliability becomes harder to maintain
Solution Approach 1:
The patent segments the source and drain regions into multiple epitaxial layers with different compositions (e.g., SiGe and Si layers) and doping types (n-type and p-type), allowing independent optimization of each layer's properties to manage fabrication complexity while maintaining high functional density
Solution Approach 2:
The patent applies local quality by creating regions with different material compositions and doping concentrations within the semiconductor structure, such as SiGe layers in contact regions and pure Si layers in channel regions, to optimize local electrical properties without increasing overall device complexity
2Ease of manufacture
If epitaxial structure growth is allowed to proceed freely, then manufacturing process is simpler, but lateral growth increases parasitic capacitance and degrades electrical performance
Solution Approach 1:
The patent performs preliminary action by forming spacer structures (inner and outer spacers) before the epitaxial growth step, which pre-establish the lateral boundaries that will confine the epitaxial structure growth and prevent excessive lateral expansion that would increase parasitic capacitance
Solution Approach 2:
The patent changes physical parameters by creating an air gap between the inner and outer spacer structures, which modifies the growth environment to confine lateral epitaxial growth while maintaining vertical growth, thereby reducing parasitic capacitance without significantly complicating the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the lateral growth of the epitaxial structure, enlarges the merge window of growths, and minimizes parasitic capacitance, thereby enhancing the electrical performance and reliability of the semiconductor device.
Implementation Method 1
an epitaxial structure is formed on the first fin and the second fin
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a first fin and a second fin on a semiconductor substrate. The semiconductor structure also includes an epitaxial structure on the first fin and the second fin. The semiconductor structure further includes outer spacers on outer sidewalls of the epitaxial structure. In addition, the semiconductor structure includes an inner spacer structure between the first fin and the second fin and covering inner sidewalls of the epitaxial structure. A top surface of the inner spacer structure is exposed to an air gap formed between the epitaxial structure and the inner spacer structure.