Epitaxial FinFET Fin Structure With Buffer-Capped Contact Geometry
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down semiconductor devices like MOSFETs and finFETs, leading to increased complexity in manufacturing processes, particularly in achieving the desired dimensions and configurations of contact areas and volume of fin structures without compromising performance.
Innovation Solution
The method involves forming epitaxial fin structures with epitaxial buffer and capping regions, using selective epitaxial growth to control the dimensions and doping concentrations of fin regions, and employing a buffer region to protect the top surface during etching processes, allowing for improved trade-offs between contact area and volume configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional scaling down methods are used to reduce device dimensions, then smaller device size is achieved, but manufacturing process complexity increases
Solution Approach 1:
The fin structure is divided into multiple epitaxial regions with different doping concentrations and compositions (e.g., SiGe buffer region, Si capping region, heavily doped source/drain regions). This segmentation allows each region to be optimized independently for its specific function, enabling precise control over electrical characteristics while simplifying the overall manufacturing process by using selective epitaxial growth rather than multiple complex processing steps
Solution Approach 2:
The patent changes material parameters by forming epitaxial regions with varying doping concentrations (e.g., 1E19 to 1E21 atoms/cm³), compositions (Si, SiGe with different Ge percentages), and thicknesses. These parameter variations enable control over carrier mobility, threshold voltage, and contact resistance, achieving high-performance devices at scaled dimensions without increasing process complexity
2Manufacturing precision
If selective epitaxial growth is used to control fin region dimensions, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The buffer region is formed preliminarily before the capping region and source/drain regions. This preliminary action establishes a foundation that controls subsequent epitaxial growth, ensuring precise dimension control of the fin structure while simplifying the overall process by pre-defining the growth template and doping profile
Solution Approach 2:
The epitaxial structure is organized in nested layers: the SiGe buffer region is nested within the Si capping region, which in turn contains the source/drain regions. This nested structure allows precise control of each layer's dimensions and properties while maintaining a relatively simple manufacturing process through sequential epitaxial growth steps
3Reliability
If buffer region is used to protect top surface during etching, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The buffer region acts as an intermediary protective layer between the etching process and the top surface of the fin structure. This intermediate layer absorbs the mechanical stress and chemical exposure during etching, protecting the underlying structure while allowing precise etching of surrounding areas without compromising the top surface integrity
Solution Approach 2:
The buffer region provides beforehand cushioning by being formed prior to the etching process. This pre-formed layer cushions the top surface against etching damage, allowing greater process margins and reducing the precision requirements for subsequent etching steps while ensuring reliable protection of the fin structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of finFETs with optimized dimensions and configurations, enhancing carrier mobility and reducing the complexity of manufacturing processes while maintaining performance, thereby addressing the scaling challenges in semiconductor devices.
Implementation Method 1
selective epitaxial growth to control the dimensions and doping concentrations of fin regions
Implementation Method 2
doping concentrations of fin regions
Data Source
AI summary
A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.