Epitaxial Gate Formation for Semiconductor Devices
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Solution Overview
Problem
Existing semiconductor manufacturing processes, such as gate-first and gate-last methods, face limitations in designing compact and efficient transistors due to adverse effects on the gate-channel interface and inefficient doping processes, particularly for III/V materials, which restrict design flexibility and increase complexity.
Innovation Solution
A process involving epitaxial growth of a contact layer and a support layer, where the support layer is etched at a higher rate than the contact layer, allows for self-aligned gate formation without etch stop layers, enabling reduced series resistance and capacitive coupling, and providing design flexibility for shorter gate lengths and increased gate size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate-first process is used to achieve self-aligned gate formation, then alignment between gate and channel region is improved, but the gate-channel interface is adversely affected by high temperature processing
Solution Approach 1:
The gate structure is formed preliminarily during the epitaxial growth process before source and drain regions are created. The gate is defined by masking the channel layer prior to contact layer growth, establishing self-alignment before any high-temperature processing occurs. This preliminary gate formation avoids subsequent interface degradation issues.
Solution Approach 2:
The conventional sequence is inverted: instead of forming gate after source/drain regions (gate-last) or forming gate first then dealing with interface issues (gate-first), the invention forms the gate structure during the epitaxial growth process itself, combining the benefits of both approaches while avoiding their drawbacks.
2Productivity
If ion implantation is used for doping source and drain regions, then doping efficiency is improved for some materials, but contact material quality deteriorates in III/V materials
Solution Approach 1:
The mechanical ion implantation process is replaced with in-situ epitaxial growth for doping the contact layers. This substitution eliminates implantation damage to III/V material interfaces while achieving efficient doping through the epitaxial process, which is naturally compatible with these materials.
3Manufacturing precision
If dummy gate structure is used in gate-last method to achieve self-aligned gate, then gate-channel alignment is improved, but design flexibility is reduced due to constraints on gate height and length
Solution Approach 1:
The dummy gate structure constraint is eliminated by directly forming the functional gate during epitaxial growth. The gate is created by masking the channel layer and growing contact layers on exposed regions, then removing the mask to define the gate structure without requiring a separate dummy gate that limits design options.
Solution Approach 2:
The gate structure is preliminarily defined during the epitaxial growth process itself, allowing direct control over gate dimensions without the constraints imposed by dummy gate aspect ratios. This preliminary definition enables flexible gate length and height design.
4Ease of operation
If multiple separate processes (depositing dielectric layer and planarizing) are used before gate formation, then gate accessibility is improved, but process complexity increases
Solution Approach 1:
Multiple separate processes are merged into the single epitaxial growth step. The gate structure, contact layers, and channel definition are all established during the epitaxial growth process rather than through separate deposition and planarization steps, significantly reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables the fabrication of high-frequency compatible semiconductor devices with reduced resistance and increased design flexibility, allowing for the formation of transistors with shorter gate lengths and larger gate sizes, addressing the limitations of previous methods.
Implementation Method 1
epitaxially growing a contact layer in contact with the channel layer, epitaxially growing a support layer on the contact layer
Data Source
AI summary
According to one aspect of the inventive concept there is provided a process for manufacturing a semiconductor device, comprising: providing a channel layer (104), providing a mask (106) on the channel layer, epitaxially growing a contact layer (108) in contact with the channel layer, epitaxially growing a support layer (110) on the contact layer, wherein the support layer is arranged to be etched at a higher rate than the contact layer, forming a trench extending through the support layer by removing the mask, and providing a conductor (118) in the trench. There is also provided an intermediate product for the manufacture of a semiconductor device.