Epitaxial Growth Defect Reduction via Dielectric Projection

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Solution Overview

Problem

Epitaxial growth in semiconductor manufacturing often results in crystalline defects such as dislocations and stacking faults at the side edges of the grown material, leading to charge leakage and reduced electrical efficiency, and existing solutions require specific substrate orientations that may not be desirable for other technical reasons.

Innovation Solution

Creating an exposed area on the substrate with a dielectric projection that allows lateral epitaxial growth, providing stress relief and reducing dislocations and stacking faults at the side edges without necessitating a specific substrate orientation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If epitaxial growth is performed on a substrate with standard orientation, then the manufacturing process is simple and substrate orientation is not restricted, but dislocations and stacking faults form at the side edges of the grown material

Engineering Contradiction:
Improvecrystalline qualityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The method performs preliminary actions by forming a patterned dielectric layer and opening structures before epitaxial growth. This preliminary structuring creates controlled growth zones that prevent dislocation propagation from the sides, thereby improving crystalline quality without requiring substrate reorientation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention applies local quality by creating spatially varying dielectric structures with different properties in different regions. The patterned dielectric layer provides localized stress management and growth control at specific areas, allowing defect reduction at side edges while maintaining overall process simplicity

Inventive Principle:
Principle #3Local quality

2Reliability

If wafer reorientation is performed to reduce dislocations and stacking faults, then crystalline quality improves, but other technical performance requirements such as transistor optimization are compromised

Engineering Contradiction:
Improvecrystalline qualityVSAvoidsubstrate orientation flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The method segments the epitaxial growth process into controlled zones defined by the patterned dielectric structures. By dividing the growth area into specific regions with different dielectric configurations, the invention enables localized stress management that reduces dislocations without requiring global substrate reorientation, thus maintaining orientation flexibility

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patterned dielectric layer acts as an intermediary structure between the substrate and the epitaxial growth. This intermediate layer mediates the stress fields and growth dynamics, providing defect reduction functionality without imposing substrate orientation constraints, thereby preserving adaptability

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If conventional epitaxial growth is performed without side edge control, then the growth process is simple and fast, but charge leakage and electron-hole recombination occur due to crystalline defects

Engineering Contradiction:
Improvegrowth speedVSAvoidelectrical efficiency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The method performs preliminary structuring with patterned dielectric layers before initiating rapid epitaxial growth. This preliminary configuration establishes defect-preventing growth zones in advance, enabling high-speed growth without generating harmful dislocations and stacking faults that would cause charge leakage and recombination

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention changes the physical and chemical parameters of the growth environment by introducing patterned dielectric structures with specific material properties and geometries. These parameter changes create favorable conditions for high-speed growth while simultaneously suppressing defect formation, thereby maintaining both productivity and electrical efficiency

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces the occurrence and distance of dislocations and stacking faults, resulting in a smoother surface edge and improved electrical efficiency of the epitaxial material without requiring wafer reorientation.

Implementation Method 1

The lateral projection provides an area for stress relief during growth of an EPI material, thereby reducing dislocation and stacking faults at its side edges

Methodology Applied
Scientific EffectStress relief: Stress Relaxation

Implementation Method 2

Epitaxy refers to the deposition by growth of an overlayer on a crystalline substrate where the overlayer is in registration with the substrate

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9356096B2Method providing an epitaxial growth having a reduction in defects and resulting structure
Publication Date: 2016.05.31 MICRON TECHNOLOGY INC
  • US9356096B2 patent drawing
  • US9356096B2 patent drawing
  • US9356096B2 patent drawing

AI summary

Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material.