Epitaxial Layer Profile for Breakdown Voltage and Leakage Control
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Solution Overview
Problem
Current semiconductor device fabrication faces challenges in integrating high-voltage, medium-voltage, and low-voltage devices due to issues such as current leakage and control of breakdown voltage as the scale of devices continues to decrease, particularly with the integration of FinFET devices.
Innovation Solution
A method is developed for fabricating semiconductor devices by forming a first gate structure on a substrate and an adjacent epitaxial layer with a specific top surface curvature, using selective epitaxial growth to form epitaxial layers in different voltage regions, and employing a combination of processes like ion implantation, oxidation, and metal gate formation to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-voltage devices and FinFET devices are integrated on the same chip, then power switching efficiency is improved and energy loss is reduced, but current leakage increases and breakdown voltage control becomes difficult
Solution Approach 1:
The substrate is divided into multiple voltage regions (first voltage region, second voltage region, third voltage region) with different breakdown voltage requirements. Each region is independently processed with selective epitaxial growth to form epitaxial layers with specific thicknesses and doping concentrations, allowing simultaneous integration of high-voltage, medium-voltage, and low-voltage devices while preventing current leakage between regions.
Solution Approach 2:
Different epitaxial layers are grown in different voltage regions with locally optimized properties: the first epitaxial layer in the high-voltage region has greater thickness and specific doping, the second epitaxial layer in the medium-voltage region has intermediate properties, and the third epitaxial layer in the low-voltage region has thinner thickness. This local customization allows each region to operate at its optimal breakdown voltage while preventing unwanted current leakage.
2Productivity
If device scale is reduced to increase integration density, then more devices can be integrated on a single chip, but control of breakdown voltage and current leakage becomes more difficult
Solution Approach 1:
Epitaxial layers are grown in advance before device fabrication, with pre-determined thicknesses and doping profiles tailored to each voltage region's requirements. This preliminary structuring establishes the breakdown voltage characteristics before subsequent processing steps, ensuring precise control even as device dimensions are scaled down for higher integration density.
Solution Approach 2:
The patent employs selective epitaxial growth with controlled parameters (temperature, pressure, gas flow, doping concentration) to grow epitaxial layers with precisely tailored thicknesses and electrical properties in different regions. By adjusting these growth parameters, the breakdown voltage of each region can be independently controlled despite overall device scaling, maintaining manufacturing precision while increasing integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of semiconductor devices by reducing current leakage and effectively controlling breakdown voltage, enabling more efficient power switching and reducing energy loss across various voltage regions.
Implementation Method 1
forming a first epitaxial layer adjacent to the first gate structure
Implementation Method 2
employing a combination of processes like ion implantation
Data Source
AI summary
A method for fabricating a semiconductor device includes the steps of first forming a first gate structure on a substrate and then forming a first epitaxial layer adjacent to the first gate structure. Preferably, a top surface of the first epitaxial layer includes a first curve, a second curve, and a third curve connecting the first curve and the second curve, in which the first curve and the second curve include curves concave downward while the third curve includes a curve concave upward.