Epitaxial Layer Formation for DRAM Junction Leakage Reduction
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices, particularly for DRAM, face challenges in miniaturization due to junction leakage issues caused by silicide layers near the semiconductor substrate's surface, leading to increased parasitic capacitance and degraded high-frequency response characteristics in MOS transistors with elevated source-and-drain structures, and complicate manufacturing processes.
Innovation Solution
A method involving the formation of epitaxial layers adjacent to gate electrodes, with impurity regions having different depths and concentrations, allowing for the reduction of gate length and pitch while maintaining high-speed operation and miniaturization, by selectively forming insulating layers and introducing impurities through these epitaxial layers to create distinct impurity diffusion regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a silicide layer is formed close to the main surface of the semiconductor substrate to enable miniaturization, then the gate length can be reduced, but junction leakage increases due to defects in the silicide layer
Solution Approach 1:
The patent transitions from a two-dimensional planar structure to a three-dimensional elevated structure by forming the impurity diffusion region at a higher level than the main surface. This vertical dimensionality change allows the contact plug to be positioned closer to the gate electrode without the silicide layer defect problem, as the impurity diffusion region is elevated above the defective silicide layer plane.
Solution Approach 2:
The patent performs preliminary formation of the elevated impurity diffusion region before forming the contact plug. By pre-positioning the impurity diffusion region at an elevated level with proper spacing from the gate electrode, the contact plug can subsequently be formed at an optimized position without encountering silicide layer defects, thus preventing junction leakage in advance.
2Reliability
If the contact plug is distanced from the edge of the PN junction to prevent junction leakage, then reliability improves, but the gate length increases preventing miniaturization
Solution Approach 1:
The patent resolves this contradiction by moving the impurity diffusion region to a higher vertical dimension. This allows the contact plug to be positioned closer to the gate electrode in the horizontal plane without causing junction leakage, because the elevated impurity diffusion region is spatially separated from the defective silicide layer plane, thus enabling miniaturization while maintaining reliability.
3Adaptability or versatility
If MOS transistors with different structures are formed to satisfy diverse product demand, then adaptability improves, but manufacturing process complexity increases
Solution Approach 1:
The patent applies local quality by forming elevated impurity diffusion regions selectively in specific regions where miniaturization is required, while other regions can maintain conventional structures. This allows different transistor structures to be formed on the same substrate through localized process variations rather than completely different manufacturing processes, thus improving adaptability while controlling complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the miniaturization and diversification of DRAM by reducing parasitic capacitance, improving high-frequency response, and simplifying the manufacturing process by forming MOS transistors with different structures on the same substrate, achieving efficient contact plug formation and reduced junction leakage.
Implementation Method 1
an epitaxial growth layer 9a which is formed on either side of the gate electrode 41
Implementation Method 2
an impurity atom is diffused in the first LDD region 21a and the epitaxial growth layer 9a, thereby forming first and second impurity diffusion regions 6 and 8
Data Source
AI summary
A method of manufacturing a semiconductor device may include, but is not limited to the following processes. First and second gate electrodes are formed over a semiconductor substrate. An epitaxial layer is selectively formed over the semiconductor substrate. The epitaxial layer is adjacent to the first gate electrode. A first impurity is introduced into the semiconductor substrate through the epitaxial layer to form a first impurity region and directly into the semiconductor substrate to form a second impurity region. The first and second impurity regions are adjacent to the first and second gate electrodes, respectively. The first impurity region includes the epitaxial layer. A first bottom surface of the first impurity region is shallower in level than a second bottom surface of the second impurity region.