Epitaxial Layer Shape Control via Inert Gas Thermal Treatment

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Solution Overview

Problem

In semiconductor fabrication, the rounding of epitaxial layers during the epitaxial growth process leads to an increased gate channel length and reduced stress effect, compromising the performance of MOS transistors, particularly at advanced nodes like 65-nm and beyond.

Innovation Solution

A method involving a thermal treatment in an inert gas atmosphere at a high temperature is performed after recess formation to alter hydrogen bonding with the silicon substrate, preventing hydrogen-induced silicon migration and allowing the epitaxial layer to maintain a desired shape during subsequent growth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If selective epitaxial growth is performed directly after recess formation, then the epitaxial growth process can be completed efficiently, but the epitaxial layer rounds off and deviates from the original recess shape

Engineering Contradiction:
Improveepitaxial growth efficiencyVSAvoidepitaxial layer shape precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

A thermal treatment process is performed as a preliminary step before the epitaxial growth process. This thermal treatment modifies the bonding or adsorption relation of hydrogen to the silicon substrate, preparing the surface in advance to prevent hydrogen-induced silicon migration during subsequent epitaxial growth, thereby maintaining the recess shape precision while enabling efficient epitaxial growth.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If thermal treatment is performed in inert gas atmosphere, then hydrogen bonding is altered to prevent silicon migration, but an additional process step is required

Engineering Contradiction:
Improveepitaxial layer shape controlVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The thermal treatment process is conducted in an inert gas atmosphere (such as nitrogen or argon), which prevents unwanted chemical reactions while allowing the thermal energy to modify hydrogen bonding. This inert environment enables precise control of the thermal treatment to alter hydrogen-silicon bonding relations without introducing contaminants, thereby maintaining epitaxial layer shape control while integrating smoothly into existing fabrication processes.

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures the epitaxial layer retains a designed shape, enhancing the stress effect on the gate channel and improving transistor performance by maintaining the intended recess geometry.

Implementation Method 1

a thermal treatment process is performed on the recess in a gas atmosphere including an inert gas at a first temperature

Methodology Applied
Scientific EffectThermal treatment: Heat Treatment

Implementation Method 2

thermal treatment process is performed on the recess in a gas atmosphere including an inert gas at a first temperature to alter or modify the bonding or adsorption relation of hydrogen

Methodology Applied
Scientific EffectThermal energy: Heating

Implementation Method 3

a thermal treatment process is performed on the recess in a gas atmosphere including an inert gas

Methodology Applied
Scientific EffectInert atmosphere:

Implementation Method 4

an epitaxy growth process is performed at a second temperature to form a silicon-containing epitaxial layer in the recess

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS8324059B2Method of fabricating a semiconductor structure
Publication Date: 2012.12.04 UNITED MICROELECTRONICS CORP
  • US8324059B2 patent drawing
  • US8324059B2 patent drawing
  • US8324059B2 patent drawing

AI summary

A method of fabricating a semiconductor structure, in which after an etching process is performed to form at least one recess within a semiconductor beside a gate structure, a thermal treatment is performed on the recess in a gas atmosphere including an inert gas before a silicon-containing epitaxial layer is formed in the recess through an epitaxy growth process.