Epitaxial Layer Stack for Monolithic 3D Memory Density
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Solution Overview
Problem
Current three-dimensional memory structures, such as vertical NAND strings, face challenges in achieving high density and efficient manufacturing processes, particularly in forming monolithic memory devices with multiple levels without intervening substrates.
Innovation Solution
The development of a monolithic three-dimensional memory device structure comprising a stack of alternating epitaxial semiconductor layers and insulating layers over a single crystalline substrate, with specific epitaxial alignment and selective etching to form memory stack structures and backside cavities, enabling the creation of vertical NAND strings with improved density and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory levels are formed using conventional three-dimensional memory structures, then storage capacity increases, but manufacturing complexity and process difficulty increase significantly
Solution Approach 1:
The memory device is divided into multiple distinct layers including first epitaxial semiconductor layers, second epitaxial semiconductor layers, insulating layers, and conductive layers. Each layer serves a specific function and can be manufactured using optimized processes for that material type, reducing overall manufacturing complexity while achieving high storage capacity through vertical stacking
Solution Approach 2:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertical stacking by forming multiple memory levels in the vertical dimension. This allows storage capacity to scale by adding layers in the third dimension rather than expanding horizontally, thereby increasing density without proportionally increasing manufacturing process complexity
2Manufacturing precision
If conventional epitaxial alignment methods are used, then manufacturing precision is maintained, but production speed and efficiency decrease
Solution Approach 1:
The first and second epitaxial semiconductor layers are formed with epitaxial alignment to the crystal structure of the substrate before subsequent processing steps. This preliminary alignment establishes a precise crystallographic foundation that guides subsequent layer formation and patterning, ensuring high manufacturing precision while enabling parallel processing of multiple layers to maintain productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of high-density monolithic three-dimensional NAND string memory devices with enhanced manufacturing efficiency, achieving multiple memory levels directly on a single substrate without the need for intervening substrates, thereby improving storage capacity and operational performance.
Implementation Method 1
A stack of layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate
Data Source
AI summary
A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity. Each electrically conductive layer contains a material from a portion of a respective second epitaxial semiconductor layer.