Epitaxial MOS Device With Un-doped Buffer Layer for Channel Control
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Solution Overview
Problem
Current planar FETs fail to meet the requirements of miniaturized electronic products due to increased drain-induced barrier lowering and short channel effects, necessitating the development of non-planar Fin-FETs with improved gate-substrate overlap and channel control.
Innovation Solution
A metal oxide semiconductor (MOS) device with a substrate, gate structure, and source/drain region within an epitaxial structure that includes an un-doped buffer layer and a strained epitaxial layer, formed through a process of recess creation, buffer layer deposition, semiconductor layer formation, and epitaxial layer growth to enhance electrical performance and prevent dislocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar FET structure is used, then manufacturing process is simple, but drain-induced barrier lowering and short channel effects increase
Solution Approach 1:
The patent transitions from a planar (2D) FET structure to a Fin-FET structure with a three-dimensional channel that extends vertically. This dimensional change increases the gate-substrate overlap area and improves channel control effectiveness, reducing drain-induced barrier lowering and short channel effects while maintaining manufacturing compatibility
2Reliability
If Fin-FET structure is adopted, then gate-substrate overlap area increases, but device complexity increases
Solution Approach 1:
The Fin-FET device is divided into distinct structural segments including the substrate, gate structure, epitaxial structure with multiple layers (buffer layer, semiconductor layer, epitaxial layer), and source/drain regions. This segmentation allows each component to be optimized independently while maintaining overall functionality, managing the complexity through modular design
3Reliability
If epitaxial structure with buffer layers is formed, then dislocation is reduced, but manufacturing process complexity increases
Solution Approach 1:
Buffer layers are formed preliminarily within the epitaxial structure before the final device operation. These buffer layers (including un-doped and doped types) are prepared in advance to stabilize the lattice structure and reduce dislocation, preventing future reliability issues while the manufacturing process manages the added complexity through established epitaxial growth techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MOS device achieves superior electrical performance by reducing leakage current and stabilizing the lattice, thereby upgrading the device's performance and avoiding dislocation issues.
Implementation Method 1
The MOS device provided in the present invention can provide superior electrical performance and avoid forming dislocation
Implementation Method 2
forming an epitaxial layer on the semiconductor layer, wherein the epitaxial layer is a strained layer
Data Source
AI summary
The present invention provides a metal oxide semiconductor (MOS) device, including a substrate, a gate structure on the substrate and a source/drain region disposed in the substrate at one side of the gate structure and in at least a part of an epitaxial structure, wherein the epitaxial structure includes a first buffer layer, which is an un-doped buffer layer, including a bottom portion disposed on a bottom surface of the epitaxial structure and a sidewall portion disposed on a concave sidewall of the epitaxial structure, an epitaxial layer which is encompassed by the first buffer layer, and a semiconductor layer which is disposed between the first buffer layer and the epitaxial layer. The source/drain region is disposed in the epitaxial structure.