Epitaxial Pedestal Source for Vertical Transistor Threshold Uniformity
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving uniform threshold voltage distribution and subthreshold characteristics across select transistors in vertical NAND strings due to variations in effective gate length and doping profiles.
Innovation Solution
The implementation of epitaxial pedestal structures formed on top of the substrate source portion, aligned epitaxially with the substrate source, allows for uniform threshold voltage distribution by extending the source region into region A and maintaining a p-n junction spatially offset from the interface between the substrate and epitaxial pedestal source, thereby controlling the lateral extent of dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional doping methods are used in vertical NAND strings, then manufacturing process is simpler, but threshold voltage distribution becomes non-uniform across select transistors
Solution Approach 1:
The source region is segmented into two distinct portions: a substrate source portion and an epitaxial pedestal source portion. This segmentation allows independent optimization of each portion's doping characteristics, enabling uniform threshold voltage distribution across select transistors while maintaining manufacturing feasibility through separate formation processes.
Solution Approach 2:
The invention introduces a vertical dimension to the source region structure by adding the epitaxial pedestal portion that extends upward from the substrate source. This vertical extension creates a three-dimensional source region configuration that controls dopant diffusion laterally, thereby achieving uniform threshold voltage across transistors positioned at different lateral locations.
2Manufacturing precision
If the p-n junction is located at the substrate epitaxial pedestal interface, then doping is simpler, but effective gate length varies causing non-uniform threshold voltage
Solution Approach 1:
The p-n junction is strategically positioned within the substrate source portion, spatially offset from the substrate epitaxial pedestal interface. This local positioning creates a specific doping profile where the junction location is optimized to control lateral dopant diffusion, ensuring that the effective gate length remains uniform across all select transistors while maintaining adequate threshold voltage margins for reliable operation.
3Manufacturing precision
If dopant diffusion extends uniformly across the substrate, then doping process is simpler, but threshold voltage becomes non-uniform across different transistor positions
Solution Approach 1:
The epitaxial pedestal source portion is formed preliminarily before final doping operations. This preliminary structure serves as a diffusion barrier that pre-configures the lateral extent of dopant diffusion. By establishing this physical boundary in advance, the doping process achieves uniform threshold voltage distribution without requiring complex multi-step doping sequences or precise dosage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of threshold voltage and subthreshold characteristics across select transistors, improving the performance and reliability of vertical NAND devices by ensuring a consistent effective gate length and stable threshold voltage margin.
Implementation Method 1
an epitaxial pedestal source portion overlying, and in epitaxial alignment, with the substrate source portion
Data Source
AI summary
An alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory stack structures are formed through the alternating stack. A backside trench is formed and the sacrificial material layers are replaced with electrically conductive layers. After formation of an insulating spacer in the trench, an epitaxial pedestal structure is grown from a semiconductor portion underlying the backside trench. A source region is formed by introducing dopants into the epitaxial pedestal structure and an underlying semiconductor portion during and/or after epitaxial growth. Alternatively, the backside trench can be formed concurrently with formation of memory openings. An epitaxial pedestal structure can be formed concurrently with formation of epitaxial channel portions at the bottom of each memory opening. After formation and subsequent removal of a dummy trench fill structure in the backside trench, a source region is formed by introducing dopants into the epitaxial pedestal structure.