Epitaxial Recess Transistor Turn-On Current Integration
Solution Overview
Problem
Highly-integrated semiconductor devices face a reduction in turn-on current, leading to decreased operation speed and reliability due to the miniaturization of transistors, necessitating an increase in turn-on current without compromising integration.
Innovation Solution
A method of manufacturing semiconductor devices involving the formation of a gate pattern on a semiconductor substrate, followed by spacer formation, wet etching to create recesses with specific sidewall orientations, and epitaxial growth to enhance the transistor's turn-on current, including amorphization ion implantation, annealing, and selective wet etching to form tapered recesses filled with epitaxial patterns that provide compressive or tensile forces to the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to achieve high integration, then device integration is improved, but turn-on current decreases
Solution Approach 1:
The patent applies local quality by forming a recess in the semiconductor substrate beneath the gate electrode and filling it with a doped semiconductor material. This creates a localized region with different electrical properties (higher carrier concentration) precisely where needed to enhance the turn-on current without affecting the overall miniaturization of the transistor structure.
Solution Approach 2:
The patent introduces a vertical dimension by forming a recess into the substrate and filling it with epitaxial material. This adds depth to the source/drain structure, creating a three-dimensional configuration that increases the effective conductive path area without increasing the planar footprint, thus maintaining high integration while improving current characteristics.
2Productivity
If transistor size is reduced to achieve high integration, then device integration is improved, but operation speed decreases
Solution Approach 1:
By locally modifying the substrate structure beneath the gate with a recess filled with high-quality epitaxial material, the patent enhances carrier mobility in the critical channel region. This localized improvement in material quality directly boosts operation speed without requiring larger device dimensions.
Solution Approach 2:
The vertical recess structure provides an additional dimension for optimizing carrier transport. The epitaxially grown material in the recess offers improved crystal quality and carrier mobility, enabling faster operation while maintaining the miniaturized planar dimensions required for high integration.
3Stability of the object's composition
If amorphization element ions are implanted and annealing is performed at low temperature, then crystal structure is improved, but processing temperature is reduced
Solution Approach 1:
The patent changes the processing parameter by performing annealing at a relatively low temperature (below 500°C, preferably 300-450°C) after amorphization ion implantation. This parameter change allows the amorphous region to crystallize into a high-quality epitaxial structure without requiring high-temperature processing, thus improving crystal structure while maintaining low processing temperature.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method increases the turn-on current of transistors, thereby enhancing the operation speed and reliability of semiconductor devices while maintaining high integration levels by utilizing epitaxial patterns with tapered sidewalls to improve carrier mobility.
Implementation Method 1
implanting amorphization element ions into a semiconductor substrate to form an amorphous region in the semiconductor substrate
Implementation Method 2
annealing the amorphous region to form a phase change region in the semiconductor substrate
Implementation Method 3
wet etching the phase change region to form a first recess in the semiconductor substrate
Implementation Method 4
wet etching the first recess to form a second recess in the semiconductor substrate
Implementation Method 5
performing an epitaxial growth process to form an epitaxial pattern that fills the second recess
Data Source
AI summary
A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.