Epitaxial Region Design for Multi-Device Wafer Integration
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Solution Overview
Problem
Manufacturing CMOS devices alongside bipolar junction transistors (BJTs) and rectifiers on the same wafer is challenging due to unique performance constraints, where improvements in one device type often lead to degraded performance in others, necessitating improved manufacturing structures and methods that balance performance across different device types.
Innovation Solution
The implementation of a non-conformal dopant-rich layer on the bottoms of recesses and a blocking layer on the sidewalls, formed using specific etching and epitaxial growth processes, to reduce junction leakage and lateral dopant diffusion, allowing for simultaneous manufacturing of CMOS, BJTs, and rectifiers with enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional masking steps are added to protect different device regions, then device performance can be optimized, but manufacturing complexity and process time increase
Solution Approach 1:
The patent achieves universality by creating a multi-functional epitaxial structure that serves different device types simultaneously. The first and second epitaxial regions with different dopant concentrations are formed through a unified process sequence without requiring additional masking steps. This multi-functional structure enables CMOS, BJT, and rectifier devices to be manufactured together on the same wafer using the same process steps, simplifying manufacturing while maintaining device-specific performance optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage current in CMOS devices, increases current gain for BJTs, and enhances breakdown voltage for rectifiers, while eliminating the need for additional masking steps, thus enabling improved performance across multiple device types on a single substrate without compromising individual device characteristics.
Implementation Method 1
formed using specific etching and epitaxial growth processes
Data Source
AI summary
An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.