Source/Drain Epitaxial Reshaping for Lower FinFET Gate Leakage
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Solution Overview
Problem
The existing methods for fabricating multi-gate devices, such as FinFETs and GAA transistors, face challenges with high parasitic capacitance and leakage performance due to the larger volume of source/drain epitaxial features, which are exacerbated by sacrificial cladding layers used to reserve space for metal gate stacks.
Innovation Solution
The method involves reshaping the source/drain epitaxial features to reduce their volume and modify their profile, using a sacrificial cladding layer to increase spacing between adjacent dielectric fins, and subsequently replacing it with an inner spacer layer to improve isolation and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If sacrificial cladding layers are used to reserve space for metal gate stacks, then spacing between adjacent dielectric fins is increased, but volume of source/drain epitaxial features increases leading to high parasitic capacitance
Solution Approach 1:
The source/drain epitaxial features are segmented into multiple regions with different cross-sectional areas along the channel direction. The first region has a larger cross-sectional area for low resistance contact, while the second region has a reduced cross-sectional area to minimize parasitic capacitance with the gate stack, thus resolving the contradiction between spacing requirements and capacitance reduction.
Solution Approach 2:
Different regions of the source/drain epitaxial features are given different local qualities: the first region near the contact has high conductivity and larger volume for low resistance, while the second region adjacent to the gate has reduced volume and modified profile to minimize parasitic capacitance, allowing each region to optimize for its specific function.
2Length of stationary object
If sacrificial cladding layers are used to reserve space for metal gate stacks, then spacing between adjacent dielectric fins is increased, but leakage performance deteriorates
Solution Approach 1:
The source/drain structure is segmented into two regions: the first region provides low resistance path while the second region with reduced volume and modified profile acts as a leakage suppression zone by minimizing the interaction area with the gate stack, thus reducing off-state leakage current.
Solution Approach 2:
The cross-sectional area of the source/drain epitaxial features is modified in the vertical dimension by creating a reduced second region adjacent to the gate stack. This dimensional modification reduces the lateral extension into the gate region, thereby suppressing leakage paths without compromising the horizontal spacing between dielectric fins.
3Volume of stationary object
If volume of source/drain epitaxial features is reduced to lower parasitic capacitance, then leakage performance improves, but manufacturing complexity increases
Solution Approach 1:
The source/drain epitaxial features are grown with a predetermined two-region structure in advance, with the second region already having reduced cross-sectional area. This preliminary formation of the optimized geometry during the epitaxial growth process itself avoids the need for additional complex post-growth processing steps to achieve the desired volume reduction.
Solution Approach 2:
The cross-sectional area parameter of the source/drain epitaxial features is changed during the epitaxial growth process by modifying growth conditions or using selective masking, allowing the second region to be formed with inherently smaller dimensions. This parameter change is achieved through controllable epitaxial processes rather than complex mechanical or chemical removal steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance and suppresses leakage current between source/drain contacts and metal gate stacks, enhancing device performance.
Implementation Method 1
growing a semiconductor layer in the recess
Data Source
AI summary
A method includes forming a semiconductor fin protruding from a substrate, forming a dummy gate structure across the semiconductor fin, recessing a portion of the semiconductor fin in a region adjacent the dummy gate structure to form a recess, growing a semiconductor layer in the recess, and forming a first dielectric layer interposing the semiconductor layer and the dummy gate structure. The semiconductor layer covers at least a portion of the first dielectric layer. The method also includes modifying a shape of the semiconductor layer to expose the portion of the first dielectric layer, depositing a second dielectric layer covering the semiconductor layer and the portion of the first dielectric layer, and replacing the dummy gate structure with a metal gate structure.