Source/Drain Epitaxial Reshaping for Lower Parasitic Capacitance
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Solution Overview
Problem
In semiconductor devices, particularly in multi-gate devices with advanced technology nodes, the large volumes of source/drain epitaxial features introduce parasitic capacitance, leading to increased resistance-capacitance response time and leakage performance issues, and adjacent features often merge, causing further capacitance and performance deterioration.
Innovation Solution
The method involves reshaping the source/drain epitaxial features to reduce their volume and enlarge the lateral distance between adjacent features, using processes such as double-patterning and etching to form fins and spacers, and epitaxially growing buffer and upper epitaxial layers with controlled dopant concentrations to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain epitaxial features are grown with large volumes to ensure adequate doping and electrical performance, then electrical conductivity is improved, but parasitic capacitance increases and leakage performance deteriorates
Solution Approach 1:
The patent applies local quality by implementing different doping concentrations in different regions of the epitaxial structure. Specifically, higher dopant concentrations are used in regions requiring enhanced electrical conductivity, while lower or zero dopant concentrations are used in regions where parasitic capacitance must be minimized. This spatial variation in doping quality allows simultaneous optimization of electrical performance and capacitance control.
Solution Approach 2:
The patent segments the epitaxial growth into multiple distinct layers with different doping characteristics. The structure includes a first epitaxial layer with higher dopant concentration for electrical performance, and a second epitaxial layer with lower or zero dopant concentration for capacitance control. This segmentation allows independent optimization of electrical conductivity and parasitic capacitance in different vertical regions.
2Productivity
If device features are scaled down to increase device density, then production efficiency and cost are improved, but adjacent source/drain epitaxial features merge causing higher parasitic capacitance
Solution Approach 1:
The patent uses local quality by applying different doping concentrations to different lateral regions. Areas where feature merging occurs receive targeted doping adjustments to control the electrical and capacitive properties of the merged regions, allowing high device density while managing parasitic capacitance in critical areas.
Solution Approach 2:
The patent changes the dopant concentration parameter across different regions and layers to control feature interaction. By adjusting doping levels in response to feature merging, the patent optimizes the electrical and capacitive characteristics of merged features, enabling higher device density without proportional increases in parasitic capacitance.
3Reliability
If source/drain epitaxial features are grown with large volumes to ensure adequate electrical performance, then conductivity is improved, but leakage current between contacts and gate stacks increases
Solution Approach 1:
The patent applies local quality by implementing spatially varying doping concentrations that optimize both conductivity and leakage suppression. Regions requiring high conductivity receive appropriate doping, while regions near gate stacks and contacts use reduced or zero doping to minimize leakage pathways, achieving both electrical performance and leakage control.
Solution Approach 2:
The patent segments the epitaxial structure into functionally distinct layers, with the first layer providing conductivity through higher doping and the second layer suppressing leakage through lower or zero doping. This vertical segmentation creates a layered architecture where each layer performs its specific function independently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This reshaping reduces parasitic capacitance, prevents feature merging, and improves device performance by suppressing leakage current and enhancing gate control, thereby improving the overall efficiency and reliability of multi-gate devices.
Implementation Method 1
growing an epitaxial feature in the recess and in physical contact with the isolation feature, the epitaxial feature covering the end of the semiconductor fin from being exposed in the recess
Data Source
AI summary
A method includes forming a semiconductor fin protruding from a substrate, forming a dummy gate structure across the semiconductor fin, recessing the semiconductor fin in a region adjacent the dummy gate structure to form a recess, growing an epitaxial feature in the recess to fully covers an end of the semiconductor fin that is otherwise exposed in the recess, trimming the epitaxial feature to reduce a width of the epitaxial feature to expose again a portion of the end of the semiconductor fin in the recess, depositing a dielectric layer on the epitaxial feature and in physical contact with the exposed portion of the end of the semiconductor fin, and replacing the dummy gate structure with a metal gate structure.