Epitaxial Source/Drain Contact Profile for Lower Resistance
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Solution Overview
Problem
Current methods for forming source/drain contacts in semiconductor devices, particularly for p-type epitaxial features, face challenges in achieving uniform feature sizes and minimizing contact resistance, often resulting in damaged features and non-uniform contact areas.
Innovation Solution
A method involving the formation of a recessed profile in source/drain features through controlled epitaxial growth and etching, followed by a melting laser anneal process to create a Ge-rich region, oxidation, and the formation of a silicide layer, which enhances the contact area between the source/drain features and contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current methods of forming source/drain contacts are used, then the fabrication process is relatively simple, but contact resistance is high and contact area uniformity is poor
Solution Approach 1:
The patent applies preliminary action by forming a recessed profile in the source/drain features before contact formation. This pre-shaping of the contact area enables subsequent annealing and silicide formation to occur on a pre-prepared surface, improving contact resistance and area uniformity while managing process complexity through staged preparation
Solution Approach 2:
The patent implements local quality by creating a recessed profile specifically at the contact areas of source/drain features, while maintaining the overall feature geometry. This localized modification allows improved contact properties without fundamentally changing the entire device structure, addressing contact resistance issues without excessive complexity increase
2Productivity
If feature sizes are scaled down to increase functional density, then production efficiency increases and costs decrease, but contact resistance reduction becomes more challenging
Solution Approach 1:
The patent applies parameter changes by modifying the surface topology parameter of source/drain features through recessed profile formation. This changes the contact area geometry to enhance contact resistance performance in scaled devices, maintaining productivity benefits while addressing the worsening contact resistance challenge through geometric parameter optimization
3Manufacturing precision
If epitaxial growth and etching are used to form recessed profiles, then contact area uniformity improves, but feature damage may occur
Solution Approach 1:
The patent applies partial action by performing controlled etching to form only the necessary recessed profile depth, avoiding excessive material removal that would cause feature damage. The etching is precisely controlled to achieve sufficient contact area uniformity while stopping before damaging the underlying feature structure
Solution Approach 2:
The patent implements beforehand cushioning by forming the recessed profile with controlled depth and geometry before subsequent processing steps. This pre-prepared structure acts as a cushion that absorbs processing variations in subsequent annealing and silicide formation, preventing feature damage while maintaining contact area uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced contact resistance and improved uniformity of source/drain feature sizes, enhancing the performance and reliability of semiconductor devices by enlarging the contact area and selectively annealing the surface regions.
Implementation Method 1
a melting laser anneal process to create a Ge-rich region
Implementation Method 2
annealing the exposed portion of the epitaxial S/D feature, such that the annealing forms over a top surface of the epitaxial S/D feature a first region having a first Ge concentration
Implementation Method 3
oxidation, and the formation of a silicide layer
Data Source
AI summary
A semiconductor structure includes semiconductor fins disposed over a substrate, an epitaxial source/drain (S/D) feature disposed over the semiconductor fins, where a top surface portion of the epitaxial S/D feature includes two surfaces slanted downward toward each other at an angle, a silicide layer disposed conformally over the top portion of the epitaxial S/D feature, and an S/D contact disposed over the silicide layer, where a bottom portion of the S/D contact extends into the epitaxial S/D feature.