Epitaxial Source/Drain Depth Control for RF FinFET Capacitance
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Solution Overview
Problem
The challenge in semiconductor integrated circuits (ICs) is to reduce coupling capacitance between source/drain features and nearby gates in RF transistors while maintaining high transistor density, as increased capacitance lowers operating frequency, particularly affecting RF FinFET transistors.
Innovation Solution
The method involves forming FinFET transistors with epitaxial source/drain features that have a specific distance and depth ratio relative to the gate structure, with a higher concentration of dopants and silicon germanium, to balance coupling capacitance and carrier mobility, thereby improving frequency response and maintaining high transistor density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If epitaxial source/drain features are placed closer to the gate structure to maintain high transistor density, then device integration is improved, but coupling capacitance increases which lowers operating frequency
Solution Approach 1:
The patent applies different distance ratios for RF transistors versus logic transistors. RF transistors use a larger distance ratio (0.05-0.15 micrometers) between epitaxial source/drain features and gate structure to reduce coupling capacitance and improve frequency response, while logic transistors use a smaller distance ratio (0.02-0.08 micrometers) to maintain high transistor density. This local differentiation resolves the contradiction by optimizing each transistor type for its specific performance requirements.
2Speed
If epitaxial source/drain features are formed with higher dopant concentration to improve carrier mobility, then frequency response is enhanced, but coupling capacitance may increase
Solution Approach 1:
The patent specifies precise parameter ranges for epitaxial source/drain features including dopant concentration (1E19 to 1E21 atoms/cm³), distance ratio (0.02-0.15 micrometers), and depth ratio (0.1-0.5 micrometers). By carefully controlling these parameters, the invention achieves high carrier mobility through adequate doping while limiting coupling capacitance through optimized geometric dimensions and spacing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces coupling capacitance in RF transistors, enhancing their frequency response and carrier mobility, while ensuring acceptable performance for logic transistors, thus addressing the frequency limitations and complexity in IC manufacturing.
Implementation Method 1
The method involves forming FinFET transistors with epitaxial source/drain features that have a specific distance and depth ratio relative to the gate structure, with a higher concentration of dopants
Data Source
AI summary
A semiconductor device includes a substrate, a first fin extending from the substrate, a first gate structure over the substrate and engaging the first fin, and a first epitaxial feature partially embedded in the first fin and raised above a top surface of the first fin. The semiconductor device further includes a second fin extending from the substrate, a second gate structure over the substrate and engaging the second fin, and a second epitaxial feature partially embedded in the second fin and raised above a top surface of the second fin. A first depth of the first epitaxial feature embedded into the first fin is smaller than a second depth of the second epitaxial feature embedded into the second fin.