Low-Temperature Epitaxial S/D Extension for Scaled Transistors
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Solution Overview
Problem
Current semiconductor device scaling faces challenges such as high doping levels, short channel effects, and threshold voltage variability due to random dopant distribution, which increase complexity and cost while limiting device performance and miniaturization.
Innovation Solution
The Advanced Low Electrostatic Field Transistor (ALEFT) using implanted Source/Drain (S/D) and Selective Low Temperature Epitaxial Extension (ISD-LTSEE) technology, which allows for gate/channel length scaling below 20 nm with reduced process complexity and cost by using low temperature processing and eliminating critical implants and high temperature steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device scaling is continued to increase device density, then device density increases and cost decreases, but short channel effects and threshold voltage variability worsen due to high doping levels and random dopant distribution
Solution Approach 1:
The patent changes the fundamental parameter of doping by eliminating conventional ion implantation and high-temperature annealing steps. Instead, it uses low-temperature selective epitaxial growth (300-650°C) to form source/drain extensions, which prevents dopant diffusion and random distribution while maintaining electrical functionality. This parameter change from thermal processing to epitaxial growth resolves the threshold voltage variability issue while preserving device scaling benefits
Solution Approach 2:
The patent extracts and removes the problematic high-temperature annealing step and conventional ion implantation process from the manufacturing flow. By taking out these steps that cause dopant diffusion and random distribution, the invention eliminates the root cause of threshold voltage variability while maintaining the ability to scale devices for increased density
2Length of moving object
If new device structures and complex process steps are implemented to continue scaling, then device scaling capability improves, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent changes the processing temperature parameter to low-temperature range (300-650°C) for selective epitaxial growth, which simplifies the overall process by eliminating multiple high-temperature annealing steps and complex ion implantation sequences. This parameter change enables continued gate length scaling while reducing process complexity
Solution Approach 2:
The low-temperature selective epitaxial growth process serves multiple functions simultaneously: it forms source/drain extensions, defines channel length, and prevents dopant diffusion. This multi-functionality reduces the number of separate process steps needed, thereby simplifying the overall manufacturing process while enabling continued device scaling
3Reliability
If high temperature processing is used for conventional doping, then dopant activation is achieved, but dopant diffusion increases causing threshold voltage variability
Solution Approach 1:
The patent fundamentally changes the temperature parameter from conventional high-temperature processing (>800°C) to low-temperature selective epitaxial growth (300-650°C). This parameter change enables dopant activation through epitaxial growth rather than thermal diffusion, achieving reliable electrical activation while precisely controlling dopant distribution without excessive diffusion
Solution Approach 2:
The patent replaces the thermal diffusion mechanism with low-temperature selective epitaxial growth for dopant activation. Instead of using high-temperature thermal energy to activate dopants, the invention uses controlled epitaxial growth at low temperatures, which substitutes the thermal activation mechanism with a growth-based activation mechanism, thereby achieving both activation and precise distribution control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces short channel effects and threshold voltage variability, enabling devices to be scaled to smaller dimensions with improved performance and reduced manufacturing complexity and cost, while maintaining high yield and low cost for IoT devices.
Implementation Method 1
Selective Low Temperature Epitaxial Extension (ISD-LTSEE) technology... low temperature selective epitaxial growth or deposition (typically the post processing after selective epitaxial growth or deposition is also controlled in the temperature range of 300-650 degree centigrade)
Data Source
AI summary
Device scaling has increased the device density of integrated circuits (ICs) and reduced the cost of circuits. Today development of new device structures, use of new materials and complex process steps are implemented to continue scaling of the semiconductor devices. The added manufacturing steps and complexity have increased cost of ICs directly impacting the implementation of IoT devices that need low cost and high yields to be successful. ALEFT-ISD-LTSEE is a device that reduces the cost while improving device performance. ALEFT-ISD-LTSEE is suitable for continued scaling of gate and channel lengths while reducing impact of random threshold variation due to discrete dopants in and around the channel by elimination of implants and high temperature processing. By creating a flat field profile at the gate by use of low temperature epitaxy as source/drain extension, the short channel effects, and the impact of line edge variations of the gate are also reduced.