Epitaxial Source/Drain Profile Control for FinFET and GAA Contacts
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in controlling the epitaxial growth of source/drain regions in finFETs and GAA FETs, particularly in achieving similar heights and dimensions for n-type and p-type regions to prevent merging and ensure adequate contact resistance, which complicates the fabrication of contact structures and affects device performance.
Innovation Solution
The solution involves forming p-type and n-type source/drain regions with similar heights and larger dimensions, using diamond-shaped and oval-shaped designs respectively, and employing dielectric S/D spacers to control lateral epitaxial growth, ensuring the n-type regions have a wider width and greater lateral extension than p-type regions, with S/D spacers' heights adjusted to maintain similar top surfaces and prevent merging during epitaxial growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If n-type and p-type source/drain regions are grown with similar dimensions, then contact resistance is improved and device performance is enhanced, but controlling the epitaxial growth to prevent merging becomes more difficult
Solution Approach 1:
The patent applies segmentation by dividing the source/drain region formation into separate epitaxial growth steps for n-type and p-type regions. Each region is grown independently with controlled lateral extension, allowing precise dimensional control while preventing merging. The n-type region is grown first with a first lateral extension, then the p-type region is grown with a second lateral extension, ensuring similar final dimensions without merging issues.
Solution Approach 2:
The patent implements local quality by applying different growth conditions to different regions during epitaxial growth. The n-type source/drain region receives different growth parameters (temperature, pressure, gas flow rates, precursor ratios) compared to the p-type region, allowing each region to achieve the desired lateral extension and dimensional characteristics tailored to its specific requirements while maintaining overall device performance.
2Productivity
If source/drain regions are scaled down to meet higher storage capacity demands, then device density is improved, but controlling epitaxial growth and preventing region merging becomes more complex
Solution Approach 1:
The patent segments the epitaxial growth process into distinct stages for n-type and p-type source/drain regions, with each stage having controlled lateral extension parameters. This segmentation enables precise control at scaled dimensions by independently managing the growth of each region, preventing merging even as overall device dimensions are reduced to increase density.
Solution Approach 2:
The patent utilizes parameter changes during epitaxial growth, including temperature, pressure, gas flow rates, and precursor ratios, to control the lateral extension of source/drain regions. By dynamically adjusting these parameters during the growth process, the patent achieves precise dimensional control at scaled dimensions, enabling higher device density while maintaining manufacturability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the fabrication of semiconductor devices with p-type and n-type source/drain regions of similar heights, improving electrical contact and device performance by maintaining similar threshold voltages and carrier mobility between PFETs and NFETs, while reducing the complexity of contact structure fabrication.
Implementation Method 1
controlling the epitaxial growth of source/drain regions in finFETs and GAA FETs
Data Source
AI summary
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a first FET, and a second FET. The first FET includes first and second fin structures disposed on first and second fin bases, respectively, a first S/D region disposed on the first and second fin bases and in contact with side surfaces of the first and second fin structures, and a first pair of spacers disposed on opposite sidewalls of the first S/D region. The second FET includes third and fourth fin structures disposed on third and fourth fin bases, respectively, a second S/D region disposed on the third and fourth fin structures, and a second pair of spacers disposed on opposite sidewalls of the second S/D region. A height of the first pair of spacers is greater than a height of the second pair of spacers.