Epitaxial Semiconductor Structure Using Crystallized Nanostructure Layers
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity of fabrication processes due to decreasing feature sizes, which makes it difficult to achieve precise patterning and etching.
Innovation Solution
The use of double-patterning or multi-patterning photolithography processes combined with self-aligned techniques to create semiconductor structures with finer pitches, along with selective epitaxial growth methods to form semiconductor layers and nanostructures, allowing for the formation of FinFET and gate-all-around transistor structures with improved precision and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity increases and manufacturing reliability deteriorates
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple stages through double-patterning or multi-patterning photolithography. Instead of attempting to create all features in a single exposure step, the process segments pattern formation into sequential steps, where each step creates a portion of the final pattern. This segmentation enables precise control over each patterning stage, maintaining manufacturing reliability while achieving smaller feature sizes and higher functional density.
Solution Approach 2:
The patent employs preliminary action through self-aligned techniques where preliminary structures (such as mandrels or spacer layers) are formed first, and subsequent features are defined relative to these pre-formed structures. This preliminary positioning ensures that critical dimensions and alignments are controlled with high precision before final pattern transfer, thereby maintaining manufacturing reliability as feature sizes decrease.
2Manufacturing precision
If double-patterning or multi-patterning photolithography processes are used to achieve finer pitches, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent merges multiple patterning steps into an integrated double-patterning or multi-patterning process flow that combines photolithography, etching, and self-aligned spacer formation. By merging these operations into a coordinated sequence with self-alignment, the patent achieves fine pitch control without proportionally increasing process complexity. The self-aligned nature of the merged process automatically ensures precision without requiring additional alignment steps.
Solution Approach 2:
The patent applies self-service through self-aligned techniques where previously formed structures automatically serve as reference frames for subsequent patterning steps. The spacer layers and mandrels formed in earlier steps self-align the final pattern without requiring additional alignment machinery or complex positioning procedures. This self-service mechanism maintains manufacturing precision while limiting the increase in operational complexity.
3Manufacturing precision
If selective epitaxial growth methods are used to form semiconductor layers, then manufacturing precision improves, but process complexity increases
Solution Approach 1:
The patent applies local quality through selective epitaxial growth where semiconductor layers are grown only in specific regions with desired properties. By controlling epitaxial growth to occur selectively on certain substrate areas or with specific crystal orientations, the process achieves precise control over layer formation location, thickness, and material composition. This localized precision is achieved through targeted exposure and growth conditions rather than uniform processing across the entire wafer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of semiconductor devices with enhanced performance and reliability by achieving smaller feature sizes and improved etching selectivity, leading to better current flow and reduced parasitic capacitance.
Implementation Method 1
growing an epitaxial structure on the crystallized semiconductor layer
Implementation Method 2
annealing the continuous semiconductor layer to form a crystallized semiconductor layer
Data Source
AI summary
A semiconductor device structure and a formation method are provided. The method includes forming multiple semiconductor nanostructures and multiple dielectric nanostructures over a substrate. The semiconductor nanostructures and the dielectric nanostructures are laid out in an alternating manner. The method also includes forming inner spacers over edges of the dielectric nanostructures and forming a continuous semiconductor layer along edges of the semiconductor nanostructures and the inner spacers. The method further includes annealing the continuous semiconductor layer to form a crystallized semiconductor layer and growing an epitaxial structure on the crystallized semiconductor layer.