Epitaxial Si Support Structure for Low-Leakage 3D Memory Access Cells
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Solution Overview
Problem
In vertical three-dimensional (3D) memory devices, the use of polycrystalline silicon in access devices leads to leakage issues due to its leaky nature, while single crystal silicon cannot grow on common amorphous dielectric materials like oxides or nitrides used in transistors.
Innovation Solution
The formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si) using a silicon wafer substrate, where SiGe is grown first, followed by a thin Si layer, allowing single crystal silicon growth with minimal lattice mismatch, creating a superlattice structure for defect mitigation and improved transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polycrystalline silicon is used in access devices, then manufacturing is easier, but leakage current increases
Solution Approach 1:
The patent uses a composite structure combining silicon germanium (SiGe) and silicon (Si) in alternating epitaxial layers. The SiGe layers provide lattice mismatch compensation that enables high-quality single crystal Si growth, while the single crystal Si provides low leakage current. This composite material approach resolves the contradiction by achieving both low leakage (comparable to single crystal) and manufacturability (through epitaxial growth on amorphous dielectric).
Solution Approach 2:
The SiGe layer acts as an intermediary between the amorphous dielectric substrate and the single crystal Si channel. It provides a crystalline template that reduces lattice mismatch, enabling the growth of high-quality single crystal Si that would otherwise be impossible on amorphous substrates. This intermediary structure allows single crystal properties (low leakage) to be achieved while maintaining compatibility with standard amorphous dielectric processes.
2Object-generated harmful factors
If single crystal silicon is grown on amorphous dielectric materials, then leakage current is reduced, but growth is not possible
Solution Approach 1:
The SiGe layer serves as a crystalline intermediary that bridges the amorphous dielectric substrate and the single crystal Si channel. It provides a lattice-matched template that enables single crystal Si growth on amorphous substrates by reducing the lattice mismatch. This intermediary structure makes single crystal growth possible on amorphous dielectric materials while maintaining the low leakage current benefits of single crystal silicon.
Solution Approach 2:
The patent changes the crystallographic parameters by introducing SiGe layers with specific lattice constants that intermediate between amorphous dielectric and single crystal Si. This parameter change (lattice mismatch compensation) enables the growth of single crystal Si on amorphous substrates by reducing the interfacial energy and promoting ordered crystal growth.
3Reliability
If alternating SiGe and Si epitaxial layers are formed, then transistor performance is improved, but device complexity increases
Solution Approach 1:
The channel region is segmented into alternating layers of SiGe and Si, each with specific thicknesses and compositions. The SiGe layers (e.g., 5-50 nm thick) provide lattice mismatch compensation, while the Si layers (e.g., 50-200 nm thick) provide the active channel. This segmentation enables high-quality single crystal growth and improved transistor performance while maintaining a systematic, repeatable fabrication process through epitaxial growth.
Solution Approach 2:
The alternating SiGe/Si epitaxial structure creates a composite material system where SiGe provides structural support and lattice matching, while Si provides the active semiconductor channel with low leakage. This composite structure improves transistor performance (lower off-current, better electrostatic control) while the epitaxial growth process maintains manufacturing feasibility through a single integrated growth step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in access devices with significantly lower off-current (Ioff), better DRAM refresh requirements, reduced gate/drain induced leakage, and enhanced electrostatic control, leading to improved subthreshold slope and cost-effectiveness.
Implementation Method 1
epitaxially forming alternating layers of a silicon germanium (SiGe) material, and a silicon (Si) material, in repeating iterations to form a vertical stack
Implementation Method 2
the silicon material in the vertical stack is selectively removed to form a plurality of horizontal openings
Data Source
AI summary
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes. The horizontally oriented access devices having a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. A support structure is provided to the epitaxially grown, single crystalline Si. Horizontally oriented access lines connect to gates opposing the channel regions formed fully around every surface of the channel region as gate all around (GAA) structures separated from the channel regions by gate dielectrics. The memory cells have horizontally oriented storage nodes coupled to the second source/drain regions and vertical digit lines coupled to the first source/drain regions.