Epitaxial Si/SiGe Horizontal Access Devices for Low-Leakage 3D Memory
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Solution Overview
Problem
In vertical three-dimensional (3D) memory devices, polysilicon-based access devices suffer from leakage issues due to grain boundaries, leading to reduced performance and yield, while single crystal silicon cannot be grown on common amorphous dielectric materials used in transistors.
Innovation Solution
The formation of multiple alternating layers of epitaxially grown silicon germanium (SiGe) and silicon (Si) is used to create a superlattice structure, with silicon germanium acting as a seed for single crystal silicon growth, minimizing lattice mismatch and strain, and employing a gate all around (GAA) structure for improved electrostatic control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polycrystalline silicon is used for access devices, then manufacturing is easier, but current leakage occurs
Solution Approach 1:
The patent uses a composite structure of silicon germanium (SiGe) and silicon (Si) epitaxial layers. The SiGe layer serves as the substrate that accommodates lattice mismatch, while the Si layer forms the channel region that prevents current leakage. This composite material approach resolves the contradiction by combining materials with complementary properties: SiGe provides structural tolerance and the Si provides electrical performance.
Solution Approach 2:
The patent applies different material properties to different regions of the access device. The SiGe is specifically placed in regions where lattice accommodation is needed, while the Si is placed in the channel region where low leakage is critical. This local differentiation of material quality allows the device to achieve both ease of manufacture and low current leakage.
2Object-generated harmful factors
If single crystal silicon is used, then current leakage is reduced, but it cannot grow on common transistor materials
Solution Approach 1:
The silicon germanium (SiGe) acts as an intermediary layer between the substrate and the single crystal silicon channel. It mediates the lattice mismatch issue by providing a transition structure that allows single crystal silicon to grow epitaxially on SiGe, which itself can be grown on common transistor materials. This intermediary approach enables the use of single crystal silicon without the growth compatibility issues.
Solution Approach 2:
The patent segments the semiconductor structure into distinct epitaxial layers: a SiGe layer and a Si layer. This segmentation allows each layer to perform its specific function - SiGe for lattice accommodation and Si for low-leakage channel formation - while being manufactured through separate epitaxial growth processes that can be independently optimized.
3Productivity
If design rules are shrunk to increase memory capacity, then more memory can be fabricated, but access device performance deteriorates
Solution Approach 1:
The patent changes the material parameters (composition and structure) of the access device by using epitaxially grown SiGe/Si layers instead of conventional materials. This parameter change in material composition allows the access devices to maintain reliable performance even as design rules are shrunk to increase memory capacity, because the epitaxial structure provides better control over material properties at smaller dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly lower off-current (Ioff) and reduced gate/drain induced leakage, enhancing DRAM performance and array yield, with three orders of magnitude lower leakage current compared to traditional silicon-based access devices.
Implementation Method 1
Multiple, alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si) are formed on a silicon wafer substrate
Data Source
AI summary
Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and storage nodes formed in tiers. And, more particularly, to multiple, alternating epitaxially grown silicon germanium (SiGe) and single crystalline silicon (Si) in different thicknesses to form tiers in which to form the horizontal access devices in vertical three dimensional (3D) memory. The horizontally oriented access devices can have a first source/drain regions and a second source drain regions separated by epitaxially grown, single crystalline silicon (Si) channel regions. Horizontally oriented access lines can connect to gate all around (GAA) structures opposing the channel regions. Vertical digit lines coupled to the first source/drain regions.