Tipless Epitaxial Source/Drain Regions Without Gate Spacers
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Solution Overview
Problem
The existing semiconductor devices with strain-inducing source/drain regions are limited by the need for gate isolation spacers, which restrict the parasitic resistance-reducing and strain-inducing abilities, and tip extensions formed from the same material as the channel region do not provide additional strain.
Innovation Solution
The formation of tipless epitaxial source/drain regions directly adjacent to the gate stack, using a dielectric gate stack placeholder to inhibit material growth and eliminate the need for gate isolation spacers, allowing strain-inducing source/drain regions to be in direct contact with the gate dielectric layer, thereby optimizing strain proximity to the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate isolation spacers are used to inhibit material growth during epitaxial film growth, then material growth on gate electrode is prevented, but the location of strain-inducing source/drain regions is restricted and parasitic resistance is not sufficiently reduced
Solution Approach 1:
The invention removes gate isolation spacers from the structure entirely and replaces them with a chemically selective epitaxial growth process that inherently prevents material deposition on the gate electrode, allowing source/drain regions to be positioned directly adjacent to the gate stack
Solution Approach 2:
The invention changes the chemical parameters of the epitaxial growth process to achieve selective growth - using conditions where silicon/germanium epitaxial growth occurs only on silicon substrate surfaces and not on polysilicon or oxide surfaces, thereby eliminating the need for physical isolation spacers
2Object-affected harmful factors
If tip extensions are formed to reduce parasitic resistance, then resistance is reduced, but additional strain on channel region is not achieved because tip extensions are formed from the same material as channel region
Solution Approach 1:
The invention makes the epitaxial source/drain regions serve dual functions: they provide low parasitic resistance through direct contact with the gate dielectric layer, and they induce strain on the channel region through lattice mismatch, eliminating the need for separate tip extensions
Solution Approach 2:
The invention merges the functions of tip extensions and strain-inducing source/drain regions into a single structure - the tipless epitaxial source/drain regions that are in direct contact with the gate dielectric layer, achieving both resistance reduction and strain induction simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge carrier mobility in the channel region by increasing the strain-inducing ability of the source/drain regions and mitigates parasitic resistance, leading to improved semiconductor device performance without the need for tip extensions.
Implementation Method 1
The lattice constant of the epitaxial silicon/germanium film is greater than that of crystalline silicon by a factor of ~ 1% (for 70% Si, 30% Ge) and so strain-inducing source/drain regions 120 are comprised of a material with a larger lattice constant than that of channel region 102. Therefore, a uniaxial compressive strain, depicted by the arrows in Figure 1C, is rendered on channel region 102 in strained PMOS- FET 130, which can enhance hole mobility in the device.
Implementation Method 2
a dielectric gate stack placeholder to inhibit material growth and eliminate the need for gate isolation spacers, allowing strain-inducing source/drain regions to be in direct contact with the gate dielectric layer
Data Source
Figure 1A~1C
Figure 2
Figure 3A~3B
AI summary
A semiconductor device having an epitaxial silicon germanium source region in a first recess of the crystalline silicon substrate at a first side of the gate electrode, the epitaxial silicon germanium source region having an undercut profile of approximately 55 degrees with respect to an uppermost surface of the crystalline silicon substrate, a portion of the epitaxial silicon germanium source region in contact with a first portion of a bottommost surface of the lower silicon dioxide portion of the gate dielectric.