Epitaxial SiGe Source Structure for PMOS FinFET Contact Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In the semiconductor industry, particularly for PMOS Fin FETs, there is a challenge in achieving optimal source/drain structures with high performance and low contact resistance, as existing epitaxial growth methods struggle to efficiently form effective SiGe layers for reducing contact resistance and minimizing SiGe deposition on undesired areas.
Innovation Solution
The method involves forming multiple epitaxial layers with varying Ge concentrations, specifically a first epitaxial layer of Si1−xGex, a second epitaxial layer of Si1−yGey, and a third epitaxial layer of Si1−zGez, where z is smaller than y, followed by a silicide layer formation using metals like Ti, Co, or Ni, to create a Si, Ge, and metal alloy layer, which reduces contact resistance and suppresses SiGe deposition on unwanted areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single epitaxial layer of SiGe is formed on the source/drain region, then the contact resistance can be reduced, but SiGe deposits on undesired areas which causes manufacturing defects
Solution Approach 1:
The single epitaxial SiGe layer is segmented into multiple layers with different Ge concentrations. The first epitaxial layer has higher Ge concentration (x) for reducing contact resistance, while the second epitaxial layer has lower Ge concentration (y) to prevent unwanted deposition, where x > y. This segmentation allows each layer to perform its specific function independently.
Solution Approach 2:
Different regions of the epitaxial structure are assigned different Ge concentrations based on their functional requirements. The lower Ge concentration region (second layer) is positioned where deposition control is critical, while the higher Ge concentration region (first layer) is positioned where contact resistance reduction is most beneficial.
2Reliability
If higher Ge concentration is used in the epitaxial layer to reduce contact resistance, then contact performance improves, but unwanted SiGe deposition increases on surrounding areas
Solution Approach 1:
The epitaxial structure is divided into two layers with different Ge concentrations. The first layer contains higher Ge concentration for optimal contact resistance, while the second layer contains lower Ge concentration to minimize unwanted deposition on surrounding areas, effectively segmenting the conflicting requirements.
Solution Approach 2:
The Ge concentration parameter is changed between layers - the first epitaxial layer uses higher Ge concentration (x) to reduce contact resistance, while the second epitaxial layer uses lower Ge concentration (y) to suppress unwanted deposition, where x > y. This parameter variation resolves the contradiction between contact performance and deposition control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces contact resistance by 1% to 20% compared to traditional methods and prevents unnecessary SiGe deposition, enhancing the performance and manufacturing efficiency of PMOS Fin FETs.
Implementation Method 1
sources and drains are formed by using an epitaxial growth method
Implementation Method 2
a silicide layer formation using metals like Ti, Co, or Ni, to create a Si, Ge, and metal alloy layer
Data Source
AI summary
A method of manufacturing a source structure for a p-type metal-oxide-semiconductor (PMOS) field effect transistor (FET) is provided. In the method, a first epitaxial layer comprising Si1−xGex is formed on a source region of an FET, a second epitaxial layer comprising Si1−yGey is formed on the first epitaxial layer, a third epitaxial layer comprising Si1−zGez is formed on the second epitaxial layer. Z is smaller than y.