Epitaxial SiGe/Si Stack Deposition for Low-Defect CFET Channels
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Solution Overview
Problem
The manufacturing of vertically stacked nanosheet based complementary field effect transistors (CFETs) faces challenges in achieving a fully strained silicon germanium-silicon epitaxial stack without defects, which is crucial for preventing channel degradation in three-dimensional transistors.
Innovation Solution
A method involving multiple deposition cycles at pressures less than 10 Torr to form epitaxial stacks comprising Si1-xGex and Si layers, using a substrate processing apparatus with silicon and germanium precursor storage modules, heaters, and pressure controllers to achieve fully strained epitaxial stacks at lower temperatures, reducing defect and particle formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional deposition processes are used to form silicon germanium-silicon epitaxial stacks, then the manufacturing process can proceed with standard equipment and parameters, but the resulting stacks contain defects and misfit dislocations that cause channel degradation
Solution Approach 1:
The patent applies parameter changes by modifying the deposition pressure to ultra-low levels (10^-6 to 10^-9 Torr) and adjusting deposition temperature ranges, which fundamentally alters the growth kinetics and reduces defect formation. This parameter optimization enables the formation of fully strained silicon germanium-silicon epitaxial stacks with minimal misfit dislocations and no particle contamination, directly resolving the contradiction between reliability and manufacturing precision.
Solution Approach 2:
The patent employs periodic alternation between silicon and silicon germanium deposition cycles to form strained-layer superlattices. This periodic structural formation allows controlled strain accumulation and release, preventing misfit dislocation formation while maintaining channel quality, thus resolving the contradiction between reliability and manufacturing precision.
2Manufacturing precision
If lower deposition pressures are used to reduce defects and particles, then the quality of the epitaxial stack improves, but the process complexity and equipment requirements increase
Solution Approach 1:
The patent utilizes an inert ultra-high vacuum environment (10^-6 to 10^-9 Torr) as the deposition atmosphere, which inherently prevents particle formation and contamination without requiring additional complex filtration or purification systems. The vacuum environment itself serves as the cleanroom, simplifying the overall process complexity while achieving superior manufacturing precision.
3Productivity
If higher deposition temperatures are used to improve growth rate, then productivity increases, but defect formation and particle contamination increase
Solution Approach 1:
The patent optimizes the deposition temperature parameter within a specific range that balances growth rate and quality. By precisely controlling temperature alongside ultra-low pressure, the process achieves adequate growth rates while preventing thermally-induced particle formation and defects, thus resolving the contradiction between productivity and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of epitaxial stacks with reduced defects and improved growth rates at lower temperatures, enhancing the manufacturing of gate-all-around field effect transistor (GAA-FET) and CFET devices by minimizing misfit dislocation density and particle formation, thus reducing the risk of process throughput loss.
Implementation Method 1
performing a plurality of deposition cycles, thereby forming the epitaxial stack on the substrate
Implementation Method 2
a heater that may be configured to attain a process temperature in the process chamber
Implementation Method 3
a pressure controller that may be configured to attain process pressure in the process chamber
Data Source
AI summary
A method for epitaxially forming an epitaxial stack on a substrate is disclosed. Embodiments of the presently described method comprise performing a plurality of deposition cycles to form the epitaxial stack, whereby each of the deposition cycles comprises deposition pulses to form the individual epitaxial layers of the epitaxial stack.