Epitaxial SiGe Source/Drain Structure for Low Resistance Contacts
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in reducing source/drain resistance and stabilizing the interface between contacts and source/drain regions, particularly in FinFET devices, where integration density improvements are hindered by material limitations and process complexities.
Innovation Solution
The formation of silicon-germanium source/drain regions with multiple layers of varying germanium and boron concentrations, combined with epitaxial growth and doping techniques, is employed to reduce resistance and enhance interface stability, using processes like metal-organic CVD and in situ doping to achieve specific Ge and B concentrations in the source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to improve integration density, then more components can be integrated into a given area, but source/drain resistance increases and interface stability deteriorates
Solution Approach 1:
The patent applies local quality by creating a multi-layer source/drain structure where each layer has different material composition and doping concentrations. Specifically, the structure includes a first source/drain region with a first doping concentration and a second source/drain region with a second doping concentration, where the doping concentrations differ between layers. This allows optimization of electrical properties at different locations within the source/drain region, reducing resistance while maintaining interface stability despite reduced feature sizes.
Solution Approach 2:
The patent employs composite materials by combining multiple semiconductor layers with different compositions and properties. The source/drain structure comprises multiple layers including silicon-germanium alloys with varying germanium concentrations, and different doping materials (e.g., boron, phosphorus) at different concentrations. This composite approach enables simultaneous optimization of electrical conductivity, mechanical stress control, and interface stability, resolving the contradiction between miniaturization and reliability.
2Ease of manufacture
If conventional single-layer source/drain structures are used, then manufacturing is simpler, but resistance is higher and interface stability is poor
Solution Approach 1:
The patent applies segmentation by dividing the source/drain region into multiple discrete layers, each with specific functions. The structure includes a first source/drain layer formed at a first depth with a first doping concentration, and a second source/drain layer formed at a second depth with a second doping concentration. This segmentation allows independent optimization of each layer's electrical properties, achieving low resistance and high interface stability while maintaining manufacturability through sequential formation processes.
Solution Approach 2:
The patent utilizes parameter changes by varying multiple parameters across different layers including doping concentration, material composition (e.g., germanium content), and depth position. The first source/drain region has a first doping concentration and the second source/drain region has a second doping concentration, with these parameters systematically changed to optimize electrical performance. This approach enables precise control of resistance and interface stability without significantly complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces source/drain resistance and improves the stability of the interface between contacts and source/drain regions, enhancing the performance and integration density of FinFET devices.
Implementation Method 1
epitaxial growth and doping techniques
Implementation Method 2
metal-organic CVD
Implementation Method 3
in situ doping to achieve specific Ge and B concentrations in the source/drain regions
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.