Epitaxial Silicon Wafer Defect Reduction via Argon Annealing
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Solution Overview
Problem
The existing manufacturing methods for epitaxial silicon wafers, particularly those doped with phosphorus for low substrate resistivity, often result in the generation of dislocation defects that deteriorate the electrical characteristics of semiconductor devices due to the formation of dislocation lines and hillock defects during epitaxial film growth.
Innovation Solution
A manufacturing method involving a silicon wafer with a (100) plane inclined at a specific angle, annealed under argon gas, and subjected to prebaking to reduce micropits, followed by epitaxial film growth at controlled temperatures to minimize dislocation lines and hillock defects, ensuring a density of dislocation lines less than 10 per square centimeter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If phosphorus is doped at high concentration during single crystal growth to achieve low substrate resistivity, then the substrate resistivity is reduced to 0.9 mΩ·cm or less, but stacking faults are generated on the epitaxial film and appear as steps on the surface, significantly deteriorating Light Point Defect (LPD)
Solution Approach 1:
The silicon wafer is annealed at 1200°C to 1220°C for 30 minutes or more under argon gas atmosphere before epitaxial film growth. This preliminary annealing treatment dissolves phosphorus clusters and eliminates micropits that would otherwise serve as nucleation sites for stacking faults during subsequent epitaxial growth, thereby preventing LPD deterioration while maintaining low substrate resistivity
Solution Approach 2:
The annealing temperature is specifically controlled within the range of 1200°C to 1220°C, which is optimal for dissolving phosphorus clusters without causing excessive silicon evaporation or other adverse effects. This precise parameter control enables effective elimination of stacking fault precursors while preserving the low resistivity characteristic
2Manufacturing precision
If annealing is performed under argon gas atmosphere to eliminate stacking faults, then stacking faults are reduced, but dislocation lines may still be generated that extend to the surface and deteriorate electrical characteristics
Solution Approach 1:
The invention specifies that the (100) plane must be inclined at an angle of 0°5′ to 0°25′ with respect to the plane perpendicular to the main surface. This specific local geometric configuration reduces the generation of dislocation lines with crystal orientations in <011> directions that would extend to the surface and deteriorate electrical characteristics, while still maintaining the benefits of stacking fault reduction
3Reliability
If the silicon wafer main surface is made to which a (100) plane is inclined at a specific angle, then dislocation line generation is reduced, but the manufacturing complexity increases
Solution Approach 1:
The invention defines a specific range for the inclination angle of the (100) plane (0°5′ to 0°25′) that optimizes the reduction of dislocation lines while remaining compatible with standard semiconductor manufacturing capabilities. This parameter specification balances defect reduction with manufacturability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in an epitaxial silicon wafer with reduced dislocation defects, enhancing the electrical characteristics of semiconductor devices and enabling their efficient production.
Implementation Method 1
annealing the silicon wafer at a temperature from 1200 degrees C. to 1220 degrees C. for 30 minutes or more under argon gas atmosphere
Implementation Method 2
dissolving micropits caused by clusters of oxygen and phosphorus
Implementation Method 3
growing the epitaxial film at a growth temperature ranging from 1100 degrees C. to 1165 degrees C. on the surface of the silicon wafer
Data Source
AI summary
A manufacturing method of an epitaxial silicon wafer uses a silicon wafer containing phosphorus, having a resistivity of less than 1.0 mΩ·cm. The silicon wafer has a main surface to which a (100) plane is inclined and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°5′ to 0°25′ with respect to an axis orthogonal to the main surface. The manufacturing method includes: annealing the silicon wafer at a temperature from 1200 degrees C. to 1220 degrees C. for 30 minutes or more under argon gas atmosphere (argon-annealing step); etching a surface of the silicon wafer (prebaking step); and growing the epitaxial film at a growth temperature ranging from 1100 degrees C. to 1165 degrees C. on the surface of the silicon wafer (epitaxial film growth step).