Epitaxial Source/Drain Layout for Low-Resistance Backside Via Contact
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Solution Overview
Problem
As integrated circuits scale down, power rails experience increased voltage drop and power consumption due to reduced dimensions, necessitating improved power rail structures and reduced resistance between source/drain features and backside power rails.
Innovation Solution
The implementation of backside power rails with enlarged source/drain features interfacing via additional lateral etching to break through dielectric layers surrounding semiconductor fins, enhancing the contact area with backside vias and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If integrated circuits are scaled down, then device size is reduced, but power rail resistance increases causing increased voltage drop and power consumption
Solution Approach 1:
The patent introduces backside power rails that extend from the backside of the substrate to the frontside, creating a three-dimensional power distribution network. This adds a vertical dimension to the traditionally planar power rails, enabling power delivery through the substrate thickness and reducing reliance on scaled-down lateral power rail dimensions.
Solution Approach 2:
The power distribution is segmented into multiple independent paths: frontside power rails, backside power rails, and vertical interconnects through the substrate. This segmentation allows current to be distributed through multiple parallel pathways, reducing the effective resistance and power loss in each individual rail segment.
2Ease of manufacture
If conventional source/drain features are used, then fabrication is simpler, but contact area with backside vias is insufficient leading to high contact resistance
Solution Approach 1:
The source/drain features are formed with an enlarged lower section before the backside via formation process. This preliminary enlargement of the contact area occurs during the epitaxial growth stage, ensuring that when backside vias are subsequently formed, they have adequate contact area with the source/drain features, thereby reducing contact resistance.
Solution Approach 2:
The source/drain features exhibit non-uniform cross-sectional geometry with an enlarged lower section specifically at the interface region with backside vias, while maintaining a smaller upper section. This local quality enhancement concentrates the contact area where it is most needed for low-resistance electrical connection, without unnecessarily increasing the overall feature size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power rail resistance and increases the number of metal tracks, providing better device integration and performance by enlarging the contact area between source/drain features and backside power rails.
Implementation Method 1
epitaxial source/drain feature with enlarged lower section interfacing with backside via
Data Source
AI summary
A semiconductor structure includes an isolation structure; first and second source/drain (S/D) features over the isolation structure, defining a first direction from the first S/D feature to the second S/D feature from a top view; one or more channel layers connecting the first and the second S/D features; a gate structure between the first and the second S/D features and engaging each of the one or more channel layers; and a via structure under the first S/D feature and electrically connecting to the first S/D feature. In a cross-sectional view perpendicular to the first direction, the via structure has a profile that widens and then narrows along a bottom-up direction.