Epitaxial Source/Drain Contact Structure for Lower FinFET Resistance

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Solution Overview

Problem

As semiconductor technology advances to nanometer process nodes, FinFETs face challenges with increasing contact resistance due to the shrinking electrode contact area on the source/drain regions.

Innovation Solution

The implementation of an epitaxial source/drain structure with voids, where a first epitaxial layer with a lower Ge concentration is formed, followed by a second epitaxial layer with a higher Ge concentration, creating a void between the second epitaxial layer and the isolation insulating layer, thereby reducing contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the FinFET size is shrunk to increase device density, then device density is improved, but contact resistance increases due to reduced electrode contact area

Engineering Contradiction:
Improvedevice densityVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a vertical dimension to the contact structure by forming an epitaxial source/drain layer that protrudes upward from the substrate surface. This vertical protrusion increases the contact area in the vertical dimension, compensating for the reduction in horizontal contact area caused by device scaling. The gate structure is positioned to extend over this vertical protrusion, creating a multi-dimensional contact interface that maintains low contact resistance despite planar scaling.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The source/drain region is segmented into multiple parts: a base source/drain region in the substrate and an epitaxial source/drain layer that protrudes vertically. This segmentation allows the contact structure to interact with both the substrate and the epitaxial layer, effectively increasing the total contact area. The gate structure is also segmented to extend over the vertical protrusion, creating multiple contact interfaces.

Inventive Principle:
Principle #1Segmentation

2Length of moving object

If the electrode contact area on source/drain is reduced to scale down transistor dimensions, then transistor size is improved, but contact resistance increases

Engineering Contradiction:
Improvetransistor dimensionsVSAvoidcontact resistance
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent transitions from a two-dimensional planar contact interface to a three-dimensional vertical contact interface. The epitaxial source/drain layer protrudes vertically from the substrate, and the gate structure extends over this vertical protrusion. This dimensional change increases the contact area available for electrical connection without increasing the transistor's planar footprint, thus maintaining small transistor dimensions while reducing contact resistance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the geometric parameters of the source/drain structure by forming an epitaxial layer with controlled thickness and composition. The vertical height of the protrusion and the composition gradient of the epitaxial layer are adjusted to optimize both the contact area and the electrical properties. This parameter control allows simultaneous achievement of small transistor dimensions and low contact resistance.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively decreases contact resistance by increasing the interfacial area between the contact layer and the epitaxial source/drain layers, while also allowing for better integration with existing manufacturing processes.

Implementation Method 1

a first epitaxial layer with a lower Ge concentration is formed, followed by a second epitaxial layer with a higher Ge concentration

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS12349392B2Semiconductor device and manufacturing method thereof
Publication Date: 2025.07.01 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12349392B2 patent drawing
  • US12349392B2 patent drawing
  • US12349392B2 patent drawing

AI summary

A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.